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DRV8300DRGE Datasheet(PDF) 8 Page - Texas Instruments |
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DRV8300DRGE Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 35 page  4.8 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPD_INLx INLx Input pulldown resistance To GND, INLx in non-inverting mode 120 200 280 kΩ RPU_INLx INLx Input pullup resistance To INT_5V, INLx in inverting mode 120 200 280 kΩ RPD_MODE MODE Input pulldown resistance To GND 120 200 280 kΩ GATE DRIVERS (GHx, GLx, SHx, SLx) VGHx_LO High-side gate drive low level voltage IGLx = -100 mA; VGVDD = 12V; No FETs connected 0 0.15 0.35 V VGHx_HI High-side gate drive high level voltage (VBSTx - VGHx) IGHx = 100 mA; VGVDD = 12V; No FETs connected 0.3 0.6 1.2 V VGLx_LO Low-side gate drive low level voltage IGLx = -100 mA; VGVDD = 12V; No FETs connected 0 0.15 0.35 V VGLx_HI Low-side gate drive high level voltage (VGVDD - VGHx) IGHx = 100 mA; VGVDD = 12V; No FETs connected 0.3 0.6 1.2 V IDRIVEP_HS High-side peak source gate current GHx-SHx = 12V 400 750 1200 mA IDRIVEN_HS High-side peak sink gate current GHx-SHx = 0V 850 1500 2100 mA IDRIVEP_LS Low-side peak source gate current GLx = 12V 400 750 1200 mA IDRIVEN_LS Low-side peak sink gate current GLx = 0V 850 1500 2100 mA tPD Input to output propagation delay INHx, INLx to GHx, GLx; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx 70 125 180 ns tPD_match Matching propagation delay per phase GHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx -30 ±4 30 ns tPD_match Matching propagation delay phase to phase GHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx -30 ±4 30 ns tR_GLx GLx rise time (10% to 90%) CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V 10 24 50 ns tR_GHx GHx rise time (10% to 90%) CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V 10 24 50 ns tF_GLx GLx fall time (90% to 10%) CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V 5 12 30 ns tF_GHx GHx fall time (90% to 10%) CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V 5 12 30 ns tDEAD Gate drive dead time DT pin floating 150 215 280 ns DT pin connected to GND 150 215 280 ns 40 kΩ between DT pin and GND 150 200 260 ns 400 kΩ between DT pin and GND 1500 2000 2600 ns tPW_MIN Minimum input pulse width on INHx, INLx that changes the output on GHx, GLx 40 70 150 ns BOOTSTRAP DIODES (DRV8300D, DRV8300DI) VBOOTD Bootstrap diode forward voltage IBOOT = 100 µA 0.45 0.7 0.85 V IBOOT = 100 mA 2 2.3 3.1 V RBOOTD Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) IBOOT = 100 mA and 80 mA 11 15 25 Ω PROTECTION CIRCUITS VGVDDUV Gate Driver Supply undervoltage lockout (GVDDUV) Supply rising 4.45 4.6 4.7 V Supply falling 4.2 4.35 4.4 V VGVDDUV_HYS Gate Driver Supply UV hysteresis Rising to falling threshold 250 280 310 mV DRV8300 SLVSFG5D – SEPTEMBER 2020 – REVISED MARCH 2022 www.ti.com 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8300 |
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