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Fig 3.

Functional diagram P5CN080/P5CN144

001aae955

INTERFACE

SIGIN

SIGOUT

IO1

IO2

PROGRAMMABLE

IO 1, 2

CLK

RST_N

VDD

VSS

CIU

ISO 14443

ROM

200 KB

PROGRAM

MEMORY

SECURE_MX51 CPU

6144 B

DATA

MEMORY

EEPROM

80 KB/

144 KB

DATA AND

PROGRAM

MEMORY

CRC16

FAST

RNG

TIMERS

16-bit

T0

16-bit

T1

RAM

FameXE

ENHANCED PUBLIC

KEY

COPROCESSOR e.g.

RSA, ECC

AES

COPROCESSOR

TRIPLE-DES

COPROCESSOR

UART

ISO 7816

CLOCK

FILTER

SECURITY SENSORS

RESET GENERATION

VOLTAGE REGULATOR

MEMORY MANAGEMENT UNIT (MMU)

CLOCK

GENERATION

P5CN080 P5CN144