LM51551DSST datasheet(4/48 Pages) TI2

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7 Pin Configuration and Functions

BIAS

GATE

VCC

PGND

COMP

PGOOD

UVLO/SYNC

AGND

Figure 7-1. 12-Pin WSON DSS Package (Top View)

Table 7-1. Pin Functions

TYPE(1)

DESCRIPTION

NO.

NAME

BIAS

Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.

VCC

Output of the internal VCC regulator and supply voltage input of the MOSFET driver. Connect a

ceramic bypass capacitor from this pin to PGND.

GATE

N-channel MOSFET gate drive output. Connect directly to the gate of the N-channel MOSFET

through a short, low inductance path.

PGND

Power ground pin. Connect directly to the ground connection of the sense resistor through a low

inductance wide and short path.

Current sense input pin. Connect to the positive side of the current sense resistor through a short

path.

COMP

Output of the internal transconductance error amplifier. Connect the loop compensation components

between this pin and PGND.

AGND

Analog ground pin. Connect to the analog ground plane through a wide and short path.

Inverting input of the error amplifier. Connect a voltage divider from the output to this pin to set output

voltage in boost/SEPIC topologies. Connect the low-side feedback resistor to AGND.

Soft-start time programming pin. An external capacitor and an internal current source set the ramp

rate of the internal error amplifier reference during soft start. Connect the ground connection of the

capacitor to AGND.

Switching frequency setting pin. The switching frequency is programmed by a single resistor

between RT and AGND.

PGOOD

Power-good indicator. An open-drain output which goes low if FB is below the under voltage

threshold. Connect a pullup resistor to the system voltage rail.

UVLO/EN/

SYNC

Undervoltage lockout programming pin. The converter start-up and shutdown levels can be

programmed by connecting this pin to the supply voltage through a resistor divider. The internal clock

can be synchronized to an external clock by applying a negative pulse signal into the UVLO/EN/

SYNC pin. This pin must not be left floating. Connect to BIAS pin if not used. Connect the low-side

UVLO resistor to AGND.

—

Exposed pad of the package. The exposed pad must be connected to AGND and the large ground

copper plane to decrease thermal resistance.

(1)

G = Ground, I = Input, O = Output, P = Power

LM5155, LM51551

SNVSB75E – DECEMBER 2018 – REVISED AUGUST 2023

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