LM51551DSST datasheet(13/48 Pages) TI2

13 / 48 page

BIAS

= VSUPPLY

UVLO

VCC

GATE

2.7 V

0.52 V

2.85 V

50-µs

VCC UV delay

1.5 V

1 V

VLOAD(TARGET)

VLOAD

Shutdown

Standby

tSS

4.5 V

UVLO should be greater than

0.55 V more than 1.5µs to start-up

1.5 µs

65-µs (typical)

internal start-up delay

SS is grounded

with 2 cycles

delay

> 35 µs

VLOAD

65-µs (typical)

internal start-up delay

Figure 9-3. Boost Start-Up Waveforms Case 2: Start-Up When VCC > 4.5 V, EN Toggle After Start-Up

The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5

V (typical) when the input voltage is in the desired operating range. The values of RUVLOT and RUVLOB can be

calculated as shown in Equation 1 and Equation 2.

UVLO(FALLING)

SUPPLY(ON)

SUPPLY(OFF)

UVLO(RISING)

UVLOT

UVLO

(1)

where

• VSUPPLY(ON) is the desired start-up voltage of the converter.

• VSUPPLY(OFF) is the desired turnoff voltage of the converter.

UVLO(RISING)

UVLOT

UVLOB

SUPPLY(ON)

UVLO(RISING)

(2)

A UVLO capacitor (CUVLO) is required in case the input voltage drops below the VSUPPLY(OFF) momentarily during

the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large,

an additional series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when the

5-μA hysteresis current turns on.

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LM5155, LM51551

SNVSB75E – DECEMBER 2018 – REVISED AUGUST 2023

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