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LM74502DDFR Datasheet(PDF) 3 Page - Texas Instruments |
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LM74502DDFR Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 30 page ![]() 5 Pin Configuration and Functions 4 2 7 3 5 1 6 8 N.C VS GATE VCAP SRC EN/UVLO GND OV Figure 5-1. DDF Package 8-Pin SOT-23 LM74502, LM74502H Top View Table 5-1. LM74502, LM74502H Pin Functions PIN I/O(1) DESCRIPTION NO. NAME 1 EN/UVLO I EN/UVLO Input. Connect to VS pin for always ON operation. Can be driven externally from a micro controller I/O. Pulling the pin low below V(ENF) makes the device enter into low Iq shutdown mode. For UVLO, connect an external resistor ladder from input supply to EN/ UVLO to ground. 2 GND G Ground pin 3 N.C — No connection 4 VCAP O Charge pump output. Connect to external charge pump capacitor. 5 VS I Input power supply pin to the controller. Connect a 100-nF capacitor across VS and GND pins. 6 GATE O Gate drive output. Connect to gate of the external N-channel MOSFET. 7 OV I Adjustable overvoltage threshold input. Connect a resistor ladder from input supply to OV pin to ground. When the voltage at OV pin exceeds the overvoltage cutoff threshold then the GATE is pulled low. GATE turns ON when the OV pin voltage goes below the OVP falling threshold. Connect OV pin to ground when OV feature is not used. 8 SRC I Source pin. Connect to common source point of external back-to-back connected N-channel MOSFETs or the source pin of the high side switch MOSFET. (1) I = Input, O = Output, G = GND www.ti.com LM74502, LM74502H SNOSDE5A – DECEMBER 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LM74502 LM74502H |
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