6 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

6.1 Application Information

6.1.1 Amplifier Topology

The topology chosen for the LMC66x, shown in Figure 6-1, is unconventional compared to general-purpose op

amps. The LMC66x incorporates novel op amp design that enables a wide input common-mode range and rail

to rail output swing even when driving a large load. The input common-mode range includes ground, making the

LMC66x an excellent choice for single supply applications. While the LMC66x supports both a wide supply and

common-mode voltage range, large input common-mode voltage can cause an increase in input bias current.

16V

Differential

Front End

Ultra-Low

Bias

Rail-to-Rail

IN+

IN

OUT

LMC66x

Figure 6-1. LMC66x Circuit Topology (Each Amplifier)

The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, even with a 600Ω load.

The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, under

heavy load (600Ω) the gain is reduced as indicated in the Electrical Characteristics.

6.1.2 Compensating Input Capacitance

The high input resistance of the LMC66x op amps allows the use of large feedback and source resistor values

without losing gain accuracy due to loading. However, the circuit can be especially sensitive to the layout when

these large-value resistors are used.

Every amplifier has some capacitance between each input and ac ground, and also some differential

capacitance between the inputs. When the feedback network around an amplifier is resistive, this input

capacitance (along with any additional capacitance due to circuit board traces, the socket, and so on) and

the feedback resistors create a pole in the feedback path. In Figure 6-2, the frequency of this pole is:

fp=  12πRPCS

(1)

where

• CS is the total capacitance at the inverting input, including amplifier input capacitance and any stray

capacitance from the IC socket (if one is used), circuit board traces, and so on.

• RP is the parallel combination of RF and RIN.

This formula, as well as the next formula, apply to inverting and noninverting op amp configurations.

When the feedback resistors are smaller than a few kΩ, the frequency of the feedback pole can be quite high,

because CS is generally less than 10pF. If the frequency of the feedback pole is much greater than the ideal

closed-loop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole can have a negligible

effect on stability, as only a small amount of phase shift is added.

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SNOSC51D – MARCH 1998 – REVISED FEBRUARY 2024

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