STA1095 datasheet(14/127 Pages) STMICROELECTRONICS

14 / 127 page

System description

STA108x, STA109x

14/127

DS13319 Rev 2

In order to generate multiple sampling rate audio frequencies, a dedicated fractional PLL is

also provided. This PLL also allows an efficient implementation of iPOD playback, by

dynamically adjusting the reconstructed audio sampling rate without CPU overload.

2.4.3

Sound DSP

Accordo2 is equipped with three (3) 150 MIPS DSPs (for a total of 450 MIPS) dedicated to

sound processing, fully integrated with the sound subsystem with a specific isochronous

bus. DSPs are provided with an integrated sound processing library implementing effects

like Spatialization, Balancing and Equalizer.

The DSP Core is a 24-bit fixed point Harvard architecture and is equipped with:

–

6 k x 32 bit (64 kByte) program PRAM

–

4 k x 24 bit (18 kByte) data XRAM

–

4 k x 24 bit (18 kByte) data YRAM

Each DSP is connected to other DSPs and audio peripherals by means of an isochronous

bus infrastructure which guarantees a controlled throughput and latency for all audio

transfers.

2.5

SDMMC

Accordo2 is equipped with 2 SDMMC controllers, allowing mass storage devices or Wi-Fi

modems.

Both interfaces implement the following specification:



eMMC - MultiMedia Card 4.4

–

26/52 MHz

–

1,4,8 bit of data



SD/SDIO 4.0

–

4 bit interface

–

SDSC/SDHC/SDXC limited to 50MHz SDR freq.

Both interfaces can be used in conjunction with DMA to efficiently implement data transfer

with minimal CPU load for handling interrupts.

2.6

DMA

DMA is designed to efficiently perform memory to memory, and memory to peripherals

transfers, offloading such tasks from the processor, thus reducing interrupt handling load.

DMA provides 16 independent channels which can be dynamically assigned to different

data-paths. Complex Scatter/gather transfers can be implemented by programming specific

DMA command linked lists.

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