LOG114 datasheet(26/43 Pages) TI2

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7.3 Power Supply Recommendations

To reduce the influence of lead inductance of power-supply lines, TI recommends that each supply be bypassed

with a 0.1μF ceramic capacitor. Connect these capacitors as close to the LOG114 supply pins to ground as

possible to improve supply-related noise rejection. A single bypass capacitor from V+ to ground is applicable for

single-supply applications.

7.4 Layout

7.4.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good printed circuit board (PCB) layout practices, including:

• Make sure that both input paths of the secondary amplifier are symmetrical and well-matched for source

impedance and capacitance to avoid converting common-mode signals into differential signals and thermal

electromotive forces (EMFs).

• Noise can propagate into analog circuitry through the power pins of the device and of the circuit as a whole.

Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog

circuitry. Connect low-ESR, 0.1µF X7R ceramic bypass capacitors between each supply pin and ground,

placed as close as possible to the device. A single bypass capacitor from V+ to ground is applicable for

single-supply applications.

• Use a C0G (NP0) ceramic capacitor for the VCM decoupling capacitance and place as close to the VCM pin

as possible.

• For photoelectric-sensing applications, place the photodiode as close as possible to the I1 pin to minimize

parasitic inductance.

• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces.

If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

• Minimize the number of thermal junctions. Preferably, the signal path is routed within a single layer without

vias, with the traces as short as possible.

• Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not

possible, place the device so that the effects of the thermal energy source on the high and low sides of the

differential signal path are evenly matched.

• Solder the thermal pad to the PCB. For the LOG114 to properly dissipate heat and minimize leakage, connect

the thermal pad to a plane or large copper pour that is electrically connected to V–, even for low-power

applications.

– The exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.

The LOG114 comes in a QFN-16 package. This leadless package has lead contacts on all four sides of the

bottom of the package, thereby maximizing board space. An exposed leadframe die pad on the bottom of the

package enhances thermal and electrical characteristics.

QFN packages are physically small, have a smaller routing area, improved thermal performance, and improved

electrical parasitics. Additionally, the absence of external leads eliminates bent-lead issues.

The QFN package can be easily mounted using standard printed circuit board (PCB) assembly techniques. See

also QFN and SON PCB Attachment application note and Quad Flatpack No− Lead Logic Packages application

note.

LOG114

SBOS301B – MAY 2004 – REVISED MARCH 2025

www.ti.com

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