S24CS0 datasheet(18/47 Pages) SII

18 / 47 page

2-WIRE CMOS SERIAL E2PROM

S-24CS01A/02A/04A/08A

Rev.4.4_00

Seiko Instruments Inc.

7. 3 Sequential Read

When the E

2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to "1"

following a start condition both in current and random read operations, it responds with an acknowledge.

An 8-bit data is then sent from the E

2PROM synchronous to the SCL clock and the address counter is

automatically incremented at the falling edge of the SCL clock for the 8th bit data.

When the master device responds with an acknowledge, the data at the next memory address is

transmitted. Response with an acknowledge by the master device has the memory address counter in the

2PROM incremented and makes it possible to read data in succession. This is called "Sequential Read".

The master device outputs stop condition not an acknowledge , the reading of E

2PROM is ended.

Data can be read in succession in the sequential read mode. When the memory address counter reaches

the last word address, it rolls over to the first memory address.

DEVICE

ADDRESS

ADR INC

SDA

LINE

DATA(n)

DATA (n+1)

DATA (n+2)

DATA (n+x)

NO ACK from

Master Device

ADR INC

Figure 18 Sequential Read

S24CS0 Datasheet(PDF) 18 Page - Seiko Instruments Inc