IN

GND

OUT

VIN

VOUT

COUT

CIN

SD

ERROR/SENSE

CIN

VOUT

VIN

IN

OUT

ERROR/SENSE

GND

COUT

SD

4à,# = 64I=T .6#I=T /2&

64I=T = 6,I=T . 6#I=T

2

& = :8+0

. 8176;+176 + :8+0;+)0&

LP3871, LP3874

SNVS225H – FEBRUARY 2003 – REVISED JUNE 2015

www.ti.com

9 Power Supply Recommendations

9.1 Power Dissipation

LP3871 and LP3874 can deliver a continuous current of 0.8 A over the full operating temperature range. A

heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of

the application. Under all possible conditions, the junction temperature must be within the range specified under

operating conditions. The total power dissipation of the device is given by:

where

•

IGND is the operating ground current of the device (specified under Electrical Characteristics).

(1)

The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the

application, and the maximum allowable junction temperature (TJmax):

(2)

The maximum allowable value for junction to ambient thermal resistance, RθJA, can be calculated using the

formula:

(3)

10 Layout

10.1 Layout Guidelines

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.

The input and output capacitors must be directly connected to the input, output, and ground pins of the regulator

using traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and ground

pins. The regulator ground pin must be connected to the external circuit ground so that the regulator and its

capacitors have a "single point ground".

It must be noted that stability problems have been seen in applications where "vias" to an internal ground plane

were used at the ground points of the device and the input and output capacitors. This was caused by varying

ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point

ground technique for the regulator and its capacitors fixed the problem.

Since high current flows through the traces going into IN and coming from OUT, Kelvin connect the capacitor

leads to these pins so there is no voltage drop in series with the input and output capacitors.

10.2 Layout Examples

Figure 19. Layout Example for SOT-223 Package

Figure 20. Layout Example for TO-263 Package

16

Submit Documentation Feedback

Copyright © 2003–2015, Texas Instruments Incorporated

Product Folder Links: LP3871 LP3874