PCA9554A Remote 8-Bit I2C and SMBus I/O Expander With Interrupt Output and

Configuration Registers

1 Features

• I2C to Parallel Port Expander

• Open-Drain Active-Low Interrupt Output

• Operating Power-Supply Voltage Range of 2.3 V to

5.5 V

• 5-V Tolerant I/Os

• 400-kHz Fast I2C Bus

• Three Hardware Address Pins Allow up to Eight

Devices on the I2C/SMBus

• Input/Output Configuration Register

• Polarity Inversion Register

• Internal Power-On Reset

• Power-Up With All Channels Configured as Inputs

• No Glitch on Power Up

• Latched Outputs With High-Current Drive

Maximum Capability for Directly Driving LEDs

• Latch-Up Performance Exceeds 100 mA Per JESD

78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

2 Description

This 8-bit I/O expander for the two-line bidirectional

bus (I2C) is designed for 2.3-V to 5.5-V VCC operation.

It provides general-purpose remote I/O expansion for

most microcontroller families via the I2C interface

[serial clock (SCL), serial data (SDA)].

The PCA9554A consists of one 8-bit Configuration

(input or output selection), Input, Output, and Polarity

Inversion (active high or active low) registers. At

power on, the I/Os are configured as inputs with a

weak pullup to VCC. However, the system master can

enable the I/Os as either inputs or outputs by writing

to the I/O configuration bits. The data for each input

or output is kept in the corresponding Input or Output

register. The polarity of the Input Port register can

be inverted with the Polarity Inversion register. All

registers can be read by the system master.

The system master can reset the PCA9554A in the

event of a timeout or other improper operation by

utilizing the power-on reset feature, which puts the

registers in their default state and initializes the I2C/

SMBus state machine.

Device Information

PART NUMBER

PACKAGE(1)

BODY SIZE (NOM)

PCA9554A

DB (SSOP) (16)

6.20 mm × 5.30 mm

DBQ (VQFN) (16)

4.90 mm × 3.90 mm

DGV (TSSOP) (16)

3.60 mm × 4.40 mm

DW (SOIC)

10.3 mm x 7.50 mm

PW (TSSOP)

5.00 mm x 4.40 mm

RGT (VQFN)

3.00 mm x 3.00 mm

RGV (VQFN)

4.00 mm x 4.00 mm

(1)

For all available packages, see the orderable addendum at

the end of the datasheet.

DB, DBQ, DGV, DW,

OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

A0

A1

A2

P0

P1

P2

P3

GND

VCC

SDA

SCL

INT

P7

P6

P5

P4

RGV PACKAGE

(TOP VIEW)

16

6

8

2

10

P7

4

3

1

7

5

12

11

9

13

14

15

P6

INT

SCL

A2

P0

P1

P2

RGT PACKAGE

(TOP VIEW)

16

6

8

2

10

P7

4

3

1

7

5

12

11

9

13

14

15

P6

INT

SCL

A2

P0

P1

P2

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PCA9554A

SCPS127F – SEPTEMBER 2006 – REVISED MARCH 2021

Copyright © 2021 Texas Instruments Incorporated

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PCA9554A

SCPS127F – SEPTEMBER 2006 – REVISED MARCH 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.