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ICSXXXXYGLFT Datasheet(PDF) 13 Page - Integrated Circuit Systems

Part # ICSXXXXYGLFT
Description  Low Power Clock Chip for Serverworks HT2400 Servers
PDF  20 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICSXXXXYGLFT Datasheet(HTML) 13 Page - Integrated Circuit Systems

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ICS932S825
1276D—10/25/07
SMBus Table: Frequency Select and Spread Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Reserved
Reserved
RW
Reserved
Reserved
0
Bit 6
Reserved
Reserved
RW
Reserved
Reserved
0
Bit 5
Reserved
Reserved
RW
Reserved
Reserved
0
Bit 4
SS_EN
Spread Spectrum Enable
RW
Latched
Bit 3
FS3
Freq Select Bit 3
RW
0
Bit 2
FS2
Freq Select Bit 2
RW
Latched
Bit 1
FS1
Freq Select Bit 1
RW
Latched
Bit 0
FS0
Freq Select Bit 0
RW
Latched
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
REF2
Output Enable
RW
Hi-Z
Enable
1
Bit 6
REF1
Output Enable
RW
Hi-Z
Enable
1
Bit 5
REF0_RUN
Output Enable
RW
Disable (Low)
Enable
1
Bit 4
PCICLK1
Output Enable
RW
Disable (Low)
Enable
1
Bit 3
PCICLK0
Output Enable
RW
Disable (Low)
Enable
1
Bit 2
Reserved
Reserved
RW
Reserved
Reserved
1
Bit 1
48MHz_1
Output Enable
RW
Disable (Low)
Enable
1
Bit 0
48MHz_0
Output Enable
RW
Disable (Low)
Enable
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Reserved
Reserved
RW
Reserved
Reserved
0
Bit 6
CPUK8G_L(6)
RW
Disable
Enable
1
Bit 5
CPUK8G_L(5)
RW
Disable
Enable
1
Bit 4
CPUK8G_L(4)
RW
Disable
Enable
1
Bit 3
CPUK8G_L(3)
RW
Disable
Enable
1
Bit 2
CPUK8G_L(2)
RW
Disable
Enable
1
Bit 1
CPUK8G_L(1)
RW
Disable
Enable
1
Bit 0
CPUK8G_L(0)
RW
Disable
Enable
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Reserved
Reserved
RW
Reserved
Reserved
0
Bit 6
PCIe_L6
RW
Disable
Enable
1
Bit 5
PCIe_L5
RW
Disable
Enable
1
Bit 4
PCIe_L4
RW
Disable
Enable
1
Bit 3
PCIe_L3
RW
Disable
Enable
1
Bit 2
PCIe_L2
RW
Disable
Enable
1
Bit 1
PCIe_L1
RW
Disable
Enable
1
Bit 0
PCIe_L0
RW
Disable
Enable
1
Output Enable
When Disabled
CPUK8GT_L = 0
CPUK8GC_L = 0
Output Enable
When Disabled
PCIeT_L = 0
PCIeC_L = 0
38/37
33/34
31/32
25/26
23/24
Byte 0
-
-
-
43/42
Byte 3
-
40/39
Byte 2
-
47/46
45/44
59/58
57/56
53/52
51/50
-
4
6
Byte 1
5
See CPU Frequency Select
Table
-
-
-
-
29/30
17
10
9
16
-



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