Integrated

Circuit

Systems, Inc.

ICS932S422C

1412A—12/10/07

Pin Configuration

Recommended Application:

PCIe Gen 2 & FBD compliant CK410B/CK410B+ clock for

Intel-based servers

Output Features:

•

5 - 0.7V current-mode differential CPU pairs

•

4 - 0.7V current-mode differential SRC pair

•

4 - PCI (33MHz)

•

3 - PCICLK_F, (33MHz) free-running

•

1 - 48MHz

•

2 - REF, 14.318MHz

Key Specifications:

•

CPU cycle-cycle jitter: < 50ps

•

SRC cycle-cycle jitter: < 125ps

•

PCI cycle-cycle jitter: < 500ps

•

CPU output skew: < 100ps

•

SRC output skew: < 250ps

•

± 300ppm frequency accuracy on all outputs except

48MHz

•

± 100ppm frequency accuracy on 48MHz

PCIe Gen 2 main Clock for Intel-based Servers

Features/Benefits:

•

Supports spread spectrum modulation, 0 to -0.5%

down spread

•

Uses external 14.318MHz crystal and external load

capacitors for low ppm synthesis error

•

CPU clocks independent of SRC/PCI clocks

•

D2/D3 SMBus address

•

Compliant with PCIe Gen II phase noise specifications

56-pin SSOP & TSSOP

VDDPCI 1

56 FSLC/TEST_SEL

GNDPCI 2

55 REF0

PCICLK0 3

54 REF1

PCICLK1 4

53 VDDREF

PCICLK2 5

52 X1

PCICLK3 6

51 X2

GNDPCI 7

50 GNDREF

VDDPCI 8

49 FSLB/TEST_MODE

PCICLK_F0 9

48 FSLA

PCICLK_F1 10

47 VDDCPU

PCICLK_F2 11

46 CPUCLKT0

VDD48 12

45 CPUCLKC0

48MHz 13

44 VDDCPU

GND48 14

43 CPUCLKT1

VDDSRC 15

42 CPUCLKC1

NC 16

41 GNDCPU

Vtt_PwrGd#/PD 17

40 CPUCLKT2

SRCCLKC1 18

39 CPUCLKC2

SRCCLKT1 19

38 VDDCPU

GNDSRC 20

37 CPUCLKT3

SRCCLKT2 21

36 CPUCLKC3

SRCCLKC2 22

35 VDDA

SRCCLKC3 23

34 GNDA

SRCCLKT3 24

33 IREF

VDDSRC 25

32 CPUCLKT4

SRCCLKT4 26

31 CPUCLKC4

SRCCLKC4 27

30 SDATA

VDDSRC 28

29 SCLK

Functionality

FSLC

1

FSLB

1

FSLA

2

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

MHz

0

0

0

266.67

100.00

33.33

14.318

48.000

0

0

1

133.33

100.00

33.33

14.318

48.000

0

1

0

200.00

100.00

33.33

14.318

48.000

0

1

1

166.67

100.00

33.33

14.318

48.000

1

0

0

333.33

100.00

33.33

14.318

48.000

1

0

1

100.00

100.00

33.33

14.318

48.000

1

1

0

400.00

100.00

33.33

14.318

48.000

11

1

1. FSLB and FSLC are three-level inputs. Please see VIL_FS and VIH_FS

specifications in the Input/Supply/Common Output Parameters Table for

correct values. Also refer to the Test Clarification Table.

2.FSLA is a low-threshold input. Please see the VIL_FS and VIH_FS

specifications in the Input/Supply/Common Output Parameters Table for correct values.

Reserved