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ICSXXXXCGLFT Datasheet(PDF) 11 Page - Integrated Circuit Systems |
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ICSXXXXCGLFT Datasheet(HTML) 11 Page - Integrated Circuit Systems |
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11 / 21 page ![]() 11 Integrated Circuit Systems, Inc. ICS932S422C 1412A—12/10/07 SMBus Table: SRC Output Enable Register Pin # Name Control Function Type 0 1 PWD Bit 7 SRCCLK7 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 6 SRCCLK6 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 5 SRCCLK5 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 4 SRCCLK4 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 3 SRCCLK3 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 2 SRCCLK2 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 1 SRCCLK1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 0 CPUCLK4 Output Enable RW Disable-Hi-Z Enable 1 SMBus Table: CPU, REF and 48 MHz Output Enable Register Pin # Name Control Function Type 0 1 PWD Bit 7 REF1 Enable Output Enable RW Disable-Low Enable 1 Bit 6 REF0 Enable Output Enable RW Disable-Low Enable 1 Bit 5 CPUCLK3 Output Enable RW Disable-Hi-Z Enable 1 Bit 4 CPUCLK2 Output Enable RW Disable-Hi-Z Enable 1 Bit 3 0 Bit 2 CPUCLK1 Output Enable RW Disable-Hi-Z Enable 1 Bit 1 CPUCLK0 Output Enable RW Disable-Hi-Z Enable 1 Bit 0 Spread Spectrum Enable Spread Off/On RW Spread Off Spread On 0 SMBus Table: PCI and PCICLK_F Output Enable Register Pin # Name Control Function Type 0 1 PWD Bit 7 PCICLK3 Output Enable RW Disable-Low Enable 1 Bit 6 PCICLK2 Output Enable RW Disable-Low Enable 1 Bit 5 PCICLK1 Output Enable RW Disable-Low Enable 1 Bit 4 PCICLK0 Output Enable RW Disable-Low Enable 1 Bit 3 PCICLK_F2 Enable Output Enable RW Disable-Low Enable 1 Bit 2 PCICLK_F1 Enable Output Enable RW Disable-Low Enable 1 Bit 1 PCICLK_F0 Enable Output Enable RW Disable-Low Enable 1 Bit 0 48MHz Enable Output Enable RW Disable-Low Enable 1 SMBus Table: PCICLK_F and SRC Stop Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 PCICLK_F2 Stop En RW Free-Running Stoppable 1 Bit 6 PCICLK_F1 Stop En RW Free-Running Stoppable 1 Bit 5 PCICLK_F0 Stop En RW Free-Running Stoppable 1 Bit 4 SRCCLK4 Stop En RW Free-Running Stoppable 1 Bit 3 SRCCLK3 Stop En RW Free-Running Stoppable 1 Bit 2 SRCCLK2 Stop En RW Free-Running Stoppable 1 Bit 1 SRCCLK1 Stop En RW Free-Running Stoppable 1 Bit 0 0 RESERVED RESERVED Free-Running Control, Default: not affected by PCI/SRC_STOP (Byte 4, bit 5) 26,27 9 - 23,24 10 23,24 21,22 Byte 3 21,22 18,19 Byte 0 NA NA 26,27 NA 39,40 18,19 54 9 4 10 42,43 6 5 45,46 32,31 Byte 1 55 36,37 CPU, SRC, PCI Byte 2 - 11 13 3 11 |
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