L99DZ300G datasheet(45/157 Pages) STMICROELECTRONICS

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Table 48. CSN timing

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Item

tCSN_HI,min(1)

Minimum CSN HI time,

active mode

Transfer of SPI-command to Input register

0.5

μs

B.033

tCSNfail(1)

CSN low timeout

Tested by scan

B.034

1. Parameter is specified by design, not tested in production.

Figure 10. SPI transfer timing diagram

CSN high to low: DO enabled

time

DI: data will be accepted on the rising edge of CLK signal

CSN

CLK

Input

Data

DO: data will change on the falling edge of CLK signal

fault bit

new data

old data

CSN low to high: actual data is

transferred to output power switches

time

28 27 26 25

CSN high to low: DO enabled

DI: data will be accepted on the rising edge of CLK signal

time

The SPI can be driven by a microcontroller with its SPI peripheral running in the following mode: CPOL = 0 and

CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed

from the high to low transition of CLK.

Figure 11. SPI input timing

0.8 VCC

0.2 VCC

Valid

CSN

CLK

set CSN

CLKH

set CLK

CLKL

hold DI

set DI

L99DZ300G

Electrical specifications

DS13902 - Rev 11

page 45/157

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