ICS9FG1201H datasheet(11/21 Pages) IDT

11 / 21 page

IDTTM/ICSTM

Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks

ICS9FG1201H 10/22/07

ICS9FG1201H

Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks

SMBus Table: Gear PLL Frequency Control Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

Gear PLL N Div7

Bit 6

Gear PLL N Div6

Bit 5

Gear PLL N Div5

Bit 4

Gear PLL N Div4

Bit 3

Gear PLL N Div3

Bit 2

Gear PLL N Div2

Bit 1

Gear PLL N Div1

Bit 0

Gear PLL N Div0

SMBusTable: Gear PLL Output Divider Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

GoutDiv 3

Bit 2

GoutDiv 2

Bit 1

GoutDiv 1

Bit 0

GoutDiv 1

SMBusTable: Reserved Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBusTable: Reserved Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RESERVED

Byte 15

Byte 13

Byte 14

RESERVED

See Gear Output Divider

Table

Gear Output Divider

RESERVED

N Divider Programming

bits

RESERVED

See 9FG1201H M/N

programming Table

RESERVED

Byte 12

RESERVED

ICS9FG1201H Datasheet(PDF) 11 Page - Integrated Device Technology

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