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ICS844071 Datasheet(PDF) 7 Page - Integrated Device Technology |
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ICS844071 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 15 page ![]() ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR IDT™ / ICS™ LVDS CLOCK GENERATOR 7 ICS844071AG SEPTEMBER 26, 2007 Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVDS Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period Offset Voltage Setup - SCOPE Qx nQx 3.3V±10% POWER SUPPLY +– Float GND LVDS VDD VDDA Phase Noise Mask Offset Frequency f 1 f 2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Clock Outputs 20% 80% 80% 20% tR t F VOD - SCOPE Qx nQx 2.5V±5% POWER SUPPLY +– Float GND LVDS VDD VDDA t PW t PERIOD t PW t PERIOD odc = x 100% nQ Q out out LVDS DC Input ➤ VOS/∆ VOS V DD |
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