TLC5929PWPR datasheet(21/46 Pages) TI2

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SID

15A

SID

DATA

15B

DATA

15C

DATA

16C

SID

DATA

15C

DATA

16C

SID

DATA

16B

DATA

14B

DATA

16B

DATA

15B

SID

15A

DATA

16A

SID

‘0’

DATA

15C

DATA

16C

DATA

15B

DATA

16B

DATA

11C

DATA

SIN

LAT

SOUT

DATA

14B

DATA

13B

DATA

12B

DATA

SID

14A

SID

13A

SID

12A

SID

DATA15AtoDATA0A

SCLK

DATA

14C

DATA

13C

DATA

12C

DATA

14B

DATA

13B

DATA

12B

DATA

11B

DATA

16B

DATA

14B

DATA

13B

DATA

14C

DATA

13C

DATA

12C

DATA

15B

DATA

14C

DATA

13C

DATA

14B

DATA

15A

SID

14A

DATA

13A

DATA

12A

DATA

11A

SID

DATA

13B

DATA

12B

DATA

11B

DATA

10B

DATA

15B

SID

14A

SID

13A

SID

12A

SID

DATA

14B

DATA

13B

DATA

12B

DATA

11B

DATA

16B

PreviousFunctionControl Data

SID

15A

DATA

15B

High

‘1’

DATA

16B

DATA

16A

‘1’

Low

‘0’

Low

High

‘0’

DATA15A toDATA0A

DATA15BtoDATA0B

OutputOn/Off

DataLatch

(Internal)

ShiftRegister

LSBData

(Internal)

ShiftRegister

LSB+1Data

(Internal)

ShiftRegister

MSB

1Data

(Internal)

ShiftRegister

MSBData

(Internal)

FunctionControl

DataLatch

(Internal)

TLC5929

www.ti.com

SBVS159B – APRIL 2011 – REVISED JULY 2012

Function Control Data Writing

When the MSB is 1' in the 17-bit shift register, the control data latch can be updated with the lower 16 bits of

data in the shift register at the rising edge of the LAT signal after the data are stored to the shift register using

the SIN and SCLK signals. When the control data latch is updated, SID is not loaded into the shift register. The

function control data write timing is shown in Figure 24.

Figure 24. Function Control Data Write Timing

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