8.3.3 Manual Reset (MR) Input for TLV840M Only

The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR

with pulse duration longer than t MR_PW will cause the reset output to assert. After MRreturns to a logic high

(V MR_H) and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.

The minimum duration for which MRis held under V MR_L must be at least 1% of t MR_tD. Otherwise, the effective

reset delay will be shorter roughly by the difference between 1% of t MR_tD and the actual MR pulse width. For

large capacitor based delays this difference could be noticeable unless care is taken to lengthen the MR pulse

width.

MR is internally connected to VDD through a pull-up resistor R MR shown in Section 8.2. If the logic signal

controlling MR is less than VDD, then additional current flows from VDD into MR internally. For minimum current

consumption, drive MRto either VDD or GND. V MR should not be higher than VDD voltage.

VIT+

tP_HL

VHYS

VIT-

tD

VIT+

VHYS

VIT-

tMR_tD

VMR_L

Time

tMR_RES

tMR_PW

(1)

MR

VDD

RESET

VMR_H

(2)

(1) MR pulse width too small to assert RESET

(2) MR voltage not low enough to assert RESET

Figure 8-4. Timing Diagram MR and RESET (TLV840M)

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TLV840

SNVSBC3C – DECEMBER 2019 – REVISED SEPTEMBER 2020

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