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TMUX1208 Datasheet(PDF) 4 Page - Texas Instruments

Part # TMUX1208
Description  TMUX1208 5-V Bidirectional 8:1, 1-Channel Multiplexer TMUX1209 5-V Bidirectional 4:1, 2-Channel Multiplexer
PDF  37 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TMUX1208 Datasheet(HTML) 4 Page - Texas Instruments

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1
N.C.
2
S1A
3
S2A
4
S3A
9
S3B
10
S2B
11
S1B
12
VDD
Not to scale
1
A0
16
A1
2
EN
15
GND
3
N.C.
14
VDD
4
S1A
13
S1B
5
S2A
12
S2B
6
S3A
11
S3B
7
S4A
10
S4B
8
DA
9
DB
Not to scale
4
TMUX1208, TMUX1209
SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
www.ti.com
Product Folder Links: TMUX1208 TMUX1209
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
TMUX1209: PW Package
16-Pin TSSOP
Top View
TMUX1209: RSV Package
16-Pin QFN
Top View
(1)
I = input, O = output, I/O = input and output, P = power
Pin Functions TMUX1209
PIN
TYPE(1)
DESCRIPTION
NAME
TSSOP
UQFN
A0
1
15
I
Address line 0. Controls the switch configuration as shown in Table 2.
EN
2
16
I
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
the A[1:0] address inputs determine which switch is turned on.
N.C.
3
1
Not Connected
Not Connected
S1A
4
2
I/O
Source pin 1A. Can be an input or output.
S2A
5
3
I/O
Source pin 2A. Can be an input or output.
S3A
6
4
I/O
Source pin 3A. Can be an input or output.
S4A
7
5
I/O
Source pin 4A. Can be an input or output.
DA
8
6
I/O
Drain pin A. Can be an input or output.
DB
9
7
I/O
Drain pin B. Can be an input or output.
S4B
10
8
I/O
Source pin 4B. Can be an input or output.
S3B
11
9
I/O
Source pin 3B. Can be an input or output.
S2B
12
10
I/O
Source pin 2B. Can be an input or output.
S1B
13
11
I/O
Source pin 1B. Can be an input or output.
VDD
14
12
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND
15
13
P
Ground (0 V) reference
A1
16
14
I
Address line 1. Controls the switch configuration as shown in Table 2.



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