Time (5 ms/div)

OUT1 (1 V/div)

OUT2 (1 V/div)

VMON1 (500 mV/div)

VMON2(500 mV/div)

TPS3780C

VDD

SENSE1

SENSE2

OUT1

OUT2

GND

R1

R2

VPULLUP

RPU1

RPU1

0.1 F

VMON1

VDD = 5 V

R3

R4

VMON2

To a re set or enable

inpu t of the syste m

To a re set or enable

inpu t of the syste m

TPS3779, TPS3780

www.ti.com

SBVS250 – APRIL 2015

9.2 Typical Applications

9.3 Monitoring Two Separate Rails

Figure 22. Monitoring Two Separate Rails Schematic

9.3.1 Design Requirements

Table 2. Design Parameters

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

VDD

5 V

5 V

Hysteresis

10%

10%

3.3 V nominal, VMON(PG) = 2.9 V,

Monitored voltage 1

VMON(PG) = 2.908 V, VMON(UV) = 2.618 V

VMON(UV) = 2.6 V

3 V nominal, VMON(PG) = 2.6 V,

Monitored voltage 2

VMON(PG) = 2.606 V, VMON(UV) = 2.371 V

VMON(UV) = 2.4 V

Output logic voltage

3.3-V CMOS

3.3-V CMOS

9.3.2 Detailed Design Procedure

1. Select the TPS3780C. The C version is selected to satisfy the hysteresis requirement. The TPS3780 is

selected for the output logic requirement. An open-drain output allows for the output to be pulled up to a

voltage other than VDD.

2. The resistor divider values are calculated by using Equation 2 and Equation 3. For SENSE1, R1 = 1.13 M

Ω

and R2 = 787 k

Ω. For SENSE2, R3 (R1) = 681 kΩ and R4 (R2) = 576 kΩ.

9.3.3 Application Curve

Figure 23. Monitoring Two Separate Rails Curve

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