Data Sheet

LT83401/LT83402

analog.com

Rev. 0

22 of 44

If the transient performance is not critical, other passive filter solutions can be realized using a physical inductor as

a larger second L and additional output capacitance for the second C, as shown in Figure 48.

Figure 48. Additional Output Ripple Filtering Using a Second LC Filter

When designing an additional filter for further attenuation of the switching ripple, it is highly recommended to design

with LTpowerCAD® to ensure the design is stable, has a good phase margin, and provides sufficient attenuation at

the switching frequency of interest.

The Silent Switcher 3 architecture enables achieving excellent noise performance from low to high frequencies at

the output of the LT83401/LT83402 while utilizing only passive filtering.

PCB Layout Recommendations

The LT83401/LT83402 is specifically designed to minimize low-frequency (10Hz to 100kHz) noise and EMI emissions,

and maximize efficiency when switching at high frequencies. For optimal performance, the LT83401/LT83402 can

use multiple VIN bypass capacitors.

Two small capacitors are placed as close as possible to the LT83401/LT83402 VIN pins. The third capacitor, with a

larger value of 4.7μF or higher, should be placed near one of these two capacitors. For a recommended PCB layout,

see Figure 49.

For more details and PCB design files, refer to the EVAL-LT83401/EVAL-LT83402 user guide. Note that large, switched

currents flow in the LT83401/LT83402 VIN and GND pins and the input capacitors. The loops formed by the input

capacitors should be as small as possible by placing the capacitors adjacent to the VIN and GND pins. Capacitors with

small case sizes, such as 0402 or 0603, are optimal due to their low parasitic inductance. Special care must be taken

with the input capacitors to ensure they have a low-impedance return path to the IC ground. This is achieved by

placing several grounds through the GND side of the input capacitors such that the ground plane is utilized to full

advantage. This should be an unbroken ground plane with a solid connection to the exposed pad of the IC, as shown

in Figure 49.

GND

SW

OUTS

2.2µH

0.1µH

DISCRETE L

100µF

100µF

×6

OPTIONAL

VOUT

LT83401/

LT83402