LTC7151S datasheet(9/44 Pages) AD

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Data Sheet

LT83203/LT83205

analog.com

Rev. B

9 of 44

Table 3. Pin Descriptions

NAME

DESCRIPTION

A resistor is connected between the RT and ground to set the switching frequency.

The PG pin is the open-drain output of an internal comparator. PG is pulled low until

the PGFB pin is within ±7.5% of 0.5V, and there are no fault conditions. PG is pulled low

when EN/UVLO is below 0.75V, INTVCC has fallen too low, or during thermal shutdown.

PG is valid when VIN is above 2.7V.

SYNC/MODE

For the LT83203/LT83205, this pin programs three different operating modes: 1) Pulse-

Skipping Mode: Connect this pin to GND for pulse-skipping mode for improved

efficiency at light loads. 2) Forced Continuous Mode (FCM): This mode offers fast

transient response and full frequency operation over a wide load range. Connect this

pin high to INTVCC (~3.4V) or an external supply >1.5V for FCM. The part also operates in

this mode by default if this pin is left floating. 3) Synchronization Mode: Drive this pin

with a clock source to synchronize to an external frequency. During synchronization,

the part operates in forced continuous mode. The SYNC/MODE pin can be toggled

during operation to change the operating mode. Contact the factory for versions of

this part that replace the SYNC/MODE pin with a CLKOUT pin. The CLKOUT pin would

provide a 50% duty-cycle square wave of the switching frequency, 180° out-of-phase

with the internal clock of the part, with a peak-to-peak amplitude of INTVCC to GND.

4, 8

VIN

The VIN pins supply current to the LT83203/LT83205 internal circuitry and to the

internal top-side power switch. Two 0402 capacitors of 0.1µF or more should be placed

to bypass both VIN pins with the positive terminal of the input capacitor as close as

possible to the VIN pins and the negative capacitor terminal as close as possible to the

GND pins. VIN pins must also be connected with an additional local bypass capacitor of

4.7µF or more. To provide sufficient headroom for the current reference, VIN must be at

least 700mV higher than the required regulation setpoint that is programmed via the

SET pin. For example, for the required regulation setpoint of 3.3V, VIN must be at least

3.3V + 700mV = 4V or higher.

5, 7, 16

(Exposed

Pad)

GND

Ground. Place the negative terminal of the input capacitor as close to the GND pins as

possible. The exposed pads should be soldered to the PCB for good thermal

performance. If necessary due to manufacturing limitations, the exposed pad may be

left disconnected; however, the performance degrades.

The SW pin is the output of the internal power switches. Connect this pin to the

inductor. This node must be kept small on the PCB for good performance and low EMI.

BST

This pin is used to provide a drive voltage higher than the input voltage to the topside

power switch. Place a 0.1µF boost capacitor as close as possible to the IC.

INTVCC

Internal 3.4V Regulator Bypass Pin. The internal power drivers and control circuits are

current is supplied by VIN. Decouple this pin to ground with at least a 1µF low

equivalent series resistance (ESR) ceramic capacitor placed close to the IC.

EN/UVLO

A voltage at this pin greater than 0.75V enables switching, and a voltage less than

200mV is guaranteed to shut down the internal current bias and sub-regulators. The

hysteretic threshold voltage is 0.75V going up and 0.7V going down. Connect to VIN if

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