LTC7151S datasheet(22/44 Pages) AD

22 / 44 page

Data Sheet

LT83203/LT83205

analog.com

Rev. B

22 of 44

Figure 49. LT83203/LT83205 Suggested Layout

The main inductor and output capacitors should be placed on the same side of the circuit board as the IC, and their

connections should be made on that layer. The impedance of the output bulk capacitor’s return path to IC ground

should also be minimized through the generous use of ground vias. Care with ground layout prevents switching

currents from the input capacitors coupling to the output through the ground, which can introduce unintentional

perturbations onto the OUTS pin. A small capacitor may also be placed locally to decouple the OUTS pin if needed.

An additional LC filter, if used, can be placed on the other side of the circuit board for optimal EMI performance,

though this is not required. Place a local unbroken ground plane under the application circuit on the layer closest to

the surface layer. The SW and BST nodes should be as small as possible. Finally, keep the OUTS, PGFB, and RT nodes

small so that the ground traces shield them from the SW and BST nodes. The OUTS, PGFB, and RT traces should not

pass underneath the main inductor and should also be kept away from the inductor vias.

The exposed pad on the bottom of the package should be soldered to the PCB to reduce thermal resistance to

ambient. To keep thermal resistance low, extend the ground plane from the GND as much as possible and add

thermal vias to additional ground planes within the circuit board and on the bottom side.

VOUT VIA

GND VIA

RSET

CSET

CIN1

CIN2

COUT1

CIN3

RPGFB(TOP)

RPGFB(BOT)

CBST

CVCC

COUT2

VIN VIA

OTHER SIGNALS VIA

LTC7151S Datasheet(PDF) 22 Page - Analog Devices