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TPS746

SBVS337A – APRIL 2018 – REVISED DECEMBER 2018

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Application Information (continued)

When using a feed-forward capacitor (CFF), the time constant for the LDO startup is increased whereas the

power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output.

To avoid this issue, and to receive a valid PG output, make sure that the time constant of both the LDO startup

and the power-good output match, which can be done by adding a capacitor in parallel with the power-good

pullup resistor. For more information, see the Pros and Cons of Using a Feedforward Capacitor with a Low-

Dropout Regulator application report.

The state of PG is only valid when the device operates above the minimum input voltage of the device and

power-good is asserted, regardless of the output voltage state when the input voltage falls below the UVLO

threshold minus the UVLO hysteresis. When the input voltage falls below approximately 0.8 V, there is not

enough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output

pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect.

8.2 Feed-Forward Capacitor (CFF)

For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to

the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.

Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF

can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and

Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.