TPS62840DLC datasheet(12/45 Pages) TI2

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STARTUP_DELAY

Device starts switching

ramps

OUT

TPS62840

SLVSEC6D – JUNE 2019 – REVISED MARCH 2020

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8.3 Feature Description

8.3.1 Smart Enable and Shutdown

To avoid a floating input, an internal 450-kΩ resistor pulls the EN pin to GND. This prevents an uncontrolled

start-up of the device in case the EN pin cannot be driven low safely. The device is in shutdown mode when the

EN input is logic low.

The device turns on with a logic high EN signal. An internal control circuit disconnects the EN pin pulldown

resistor once the device has finished soft start and the output voltage is in regulation. With the EN pin set low,

the device enters shutdown mode and the pulldown resistor is activated again.

8.3.2 Soft Start

To protect the battery and system from excessive inrush current, the device features a soft start of the output

voltage.

Once the device has been enabled, it initializes and powers up its internal circuits. This occurs during the

regulator start-up delay time (tSTARTUP_DELAY). Once this delay expires, the device enters soft start, starts

switching, and ramps up the output voltage.

The device operates with a reduced switch current limit (ILIMF_SS) throughout the entire soft-start phase (tSS). The

switch current limit is increased to its nominal value (ILIMF) once the output voltage has reached its nominal value

or the reduced current limit soft-start time (tSS_ILIMF) has expired, whichever occurs first. The soft-start phase (tSS)

can last up to approximately 700 µs. Figure 12 shows the start-up procedure.

Figure 12. Device Start-up

8.3.3 Mode Selection: Power-Save Mode (PFM/PWM) or Forced PWM Operation (FPWM)

Connecting the MODE input to GND enables the automatic PWM and power-save mode operation. The

converter operates in PWM mode at moderate to heavy loads and in the PFM mode during light loads, which

maintains high efficiency over a wide load current range.

Pulling the MODE pin high forces the converter to operate in PWM mode even at light load currents, allowing

lower ripple compared to PFM mode switching. In this mode, the efficiency is lower compared to the power-save

mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced PWM

mode during operation. This allows efficient power management by adjusting the operation of the converter to

the specific system requirements. The MODE pin must be terminated.

This pin is not available in the YBG package, where the device automatically transitions between power-save

and PWM modes.

8.3.4 Output Voltage Selection (VSET)

The output voltage is set with a single external resistor connected between the VSET pin and GND. Once the

device has been enabled and the control logic as well as the reference system are powered up, an R2D (resistor

to digital) conversion is started to detect the value of the external RSET resistor. A pre-defined fixed output voltage

is set based on the RSET value. The output voltage is set once during the start-up delay phase of the device.

TPS62840DLC Datasheet(PDF) 12 Page - Texas Instruments

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