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DM505LRBABF Datasheet(PDF) 15 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 295 page  Copyright © 2016–2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback 15 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Table 4-1. Pin Attributes(1) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MUXMODE [8] I/O VOLTAGE VALUE [9] POWER [10] HYS [11] BUFFER TYPE [12] PULL UP/DOWN TYPE [13] DSIS [14] T21 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 0 1.2/1.35/1.5/ 1.8 vdds_ddr3 LVCMOS DDR PUx/PDy AB5 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy Y20 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 0 1.2/1.35/1.5/ 1.8 vdds_ddr3 LVCMOS DDR PUx/PDy W2 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy T22 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 0 1.2/1.35/1.5/ 1.8 vdds_ddr3 LVCMOS DDR PUx/PDy Y11 ddr1_ecc_d0 ddr1_ecc_d0 0 IO PD PD 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy AA12 ddr1_ecc_d1 ddr1_ecc_d1 0 IO PD PD 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy AA11 ddr1_ecc_d2 ddr1_ecc_d2 0 IO PD PD 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy Y9 ddr1_ecc_d3 ddr1_ecc_d3 0 IO PD PD 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy AA13 ddr1_ecc_d4 ddr1_ecc_d4 0 IO PD PD 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy AB11 ddr1_ecc_d5 ddr1_ecc_d5 0 IO PD PD 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy AA9 ddr1_ecc_d6 ddr1_ecc_d6 0 IO PD PD 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy AB9 ddr1_ecc_d7 ddr1_ecc_d7 0 IO PD PD 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy P2 ddr1_odt0 ddr1_odt0 0 O PD drive 0 (OFF) 0 1.2/1.35/1.5/ 1.8 vdds_ddr1 LVCMOS DDR PUx/PDy H1 emu0 emu0 0 IO PU PU 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD gpio4_28 14 IO Driver off 15 I H2 emu1 emu1 0 IO PU PU 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD gpio4_29 14 IO Driver off 15 I E8 gpmc_ad0 gpmc_ad0 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0 rgmii1_rxd2 1 I 0 gpio1_14 14 IO sysboot0 15 I A7 gpmc_ad1 gpmc_ad1 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0 rgmii1_rxd1 1 I 0 gpio1_15 14 IO sysboot1 15 I |
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