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DM505LRBABF Datasheet(PDF) 3 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 295 page  SPRS916_Intro_001 JTAG PLLs OSC Memory Controllers GPMC 8b/16b with up to 16b ECC LPDDR2 / DDR2/ DDR3 / DDR3L 32b with 8b ECC Timer x8 Mailbox/Spinlock 10-bit ADC Control Module EDMA GPIO x4 PWMSSx1 MMUx1 PRCM System I2C x2 SPI x4 QSPI x1 SDIO x1 DCAN with ECC UART x3 McASP x3 Serial Interfaces GMAC Connectivity EDMA 2TC L2 256KB Cache C66x L1D 32KB L1P 32KB DSP Subsystem x2 Video Input Port CAL LVDSRX CSI2 ISP Video Front End up to 512KB RAM with ECC IPU with ECC Dual Cortex M4 32KB ROM EVE 16MAC EDMA 2TC Vision Accelerator OSD Resizing CSC SD-DAC DVOUT Display Subsystem Interconnect DM505 Copyright © 2016, Texas Instruments Incorporated MCAN(CAN-FD) with ECC 3 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Device Overview Copyright © 2016–2018, Texas Instruments Incorporated 1.4 Functional Block Diagram Figure 1-1 is functional block diagram of the superset. Figure 1-1. DM505 Block Diagram |
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