DM505LRBABF datasheet(171/295 Pages) TI2

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rgmii _txc

(A)

rgmii _txd

[3:0]

(B)

rgmii _txctl

(B)

1st Half-byte

TXERR

TXEN

2nd Half-byte

[internal delay enabled]

SPRS91v_GMAC_09

171

DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.

(2) RGMII0 1000Mbps operation is not supported.

(3) RGMII1 1000Mbps operation is not supported.

TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.

Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the

rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on

rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.

Figure 5-53. GMAC Transmit Interface Timing RGMIIn operation

5.9.6.15 SDIO Controller

MMC interface is compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic SDIO devices, it

supports the following applications:

•

MMC 4-bit data, SD Default speed, SDR

•

MMC 4-bit data, SD High speed, SDR

•

MMC 4-bit data, UHS-I SDR12 (SD Standard v3.01), 4-bit data, SDR, half cycle

•

MMC 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle

NOTE

For more information, see the SDIO Controller chapter of the Device TRM.

5.9.6.15.1 MMC, SD Default Speed

Figure 5-54, Figure 5-55, Table 5-69, and Table 5-70 present Timing requirements and Switching

characteristics for MMC - SD and SDIO Default speed in receiver and transmiter mode.

Table 5-69. Timing Requirements for MMC - Default Speed Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

DS5

tsu(cmdV-clkH)

Setup time, mmc_cmd valid before mmc_clk rising clock edge

5.11

DS6

th(clkH-cmdV)

Hold time, mmc_cmd valid after mmc_clk rising clock edge

20.46

DS7

tsu(dV-clkH)

Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge

5.11

DS8

th(clkH-dV)

Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge

20.46

(1) i in [i:0] = 3

Table 5-70. Switching Characteristics for MMC - SD/SDIO Default Speed Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

DS0

fop(clk)

Operating frequency, mmc_clk

MHz

DS1

tw(clkH)

Pulse duration, mmc_clk high

0.5×P-

0.270

DM505LRBABF Datasheet(PDF) 171 Page - Texas Instruments

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