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DM505LRBABF Datasheet(PDF) 176 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 176 Page - Texas Instruments |
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176 / 295 page  176 DM505 SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2018, Texas Instruments Incorporated Table 5-77. MMC IOSETs (continued) SIGNALS IOSET1 IOSET2 IOSET3 BALL MUX BALL MUX BALL MUX mmc_dat2 E17 5 Y15 5 C20 5 mmc_dat3 F17 5 W15 5 A20 5 5.9.6.16 GPIO The general-purpose interface combines four general-purpose input/output (GPIO) banks. Each GPIO module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 126 pins. These pins can be configured for the following applications: • Data input (capture)/output (drive) • Keyboard interface with a debounce cell • Interrupt generation in active mode upon the detection of external events. Detected events are processed by two parallel independent interrupt-generation submodules to support biprocessor operations • Wake-up request generation in idle mode upon the detection of external events NOTE For more information, see the General-Purpose Interface chapter of the Device TRM. NOTE The general-purpose input/output i (i = 1 to 4) bank is also referred to as GPIOi. CAUTION The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-78. In Table 5-78 are presented the specific groupings of signals (IOSET) for use with GPIO. Table 5-78. GPIO2/3/4 IOSETs SIGNALS IOSET1 IOSET2 BALL MUX BALL MUX GPIO2 gpio2_11 J17 14 gpio2_12 K22 14 gpio2_13 K21 14 gpio2_14 K18 14 gpio2_20 AB17 14 gpio2_23 AA17 14 AA17 14 gpio2_24 U16 14 U16 14 gpio2_27 U15 14 gpio2_28 V15 14 gpio2_29 Y15 14 gpio2_30 W15 14 gpio2_31 AA15 14 |
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