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RF5198
Rev A5 DS060310
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Evaluation Board Schematic
C40
4.7
μF
VREG
VMODE
C20
4.7
μF
C10
22
μF
C3
1 nF
R1
1
0
Ω
VCC BIAS
R3
5
5.1 k
Ω
VDET
16
15
14
13
1
2
3
4
8
7
6
5
9
10
11
12
Bias
IMN
OMN
Interstage MN
Q1
Q2
Integrated
Power
Detector
C1
1 nF
J1
RF IN
R5
0
Ω
R4
6
SUT
Ω
C4
7
4.7 nF
SUT = Select Under Test
J2
RF OUT
C5
DNI
VCC2
R2
8
0
Ω
VCC1
NOTES
1. L2 is removed when VCC1 is not connected to VCC2, and R1 is placed.
5. R3 = 5.1 k
Ω typ. This load resistor determines the detector sensitivity.
An internal 15 pF capacitor is in parallel with this load resistor.
6. R4 is optional and may be used in conjunction with R5 to scale V_DET
(max) if desired.
7. C4 is used in conjunction with R3 and R5 to set the rise and fall time of
the detected output voltage, and trade-off acceptable voltage ripple
versus rise/fall time.
8. R2 is removed when VCC BIAS is not connected to VCC1,2.
C6
DNI
C2
1 nF
50
Ω μstrip
50
Ω μstrip
P2-3
P2-1
GND
VCC1
GND
VCC2
VCC BIAS
P2-4
P2
5
4
3
2
1
CON5
P1
5
4
3
2
1
CON5
GND
GND
P1-5
VDET
P1-2
VREG
P1-1
VMODE
C30
4.7
μF
L2
1
8.2 nH
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