ST7735SV datasheet(8/201 Pages) SITRONIX

8 / 201 page

ST7735SV

V 1.3

Page 8 of 201

2020-01

LIST OF FIGURES

Figure 1 Parallel Interface Timing Characteristics (8080 Ceries MCU Interface) ........................................... 31

Figure 2 Rising And Falling Timing for Input And Output Signal ..................................................................... 32

Figure 3 Chip Selection (CSX) Timing............................................................................................................. 32

Figure 4 Write-to-Read And Read-to-Write Timing ......................................................................................... 32

Figure 5 Parallel Interface Timing Characteristics (6800-Series MCU Interface) ........................................... 33

Figure 6 3-line Serial Interface Timing............................................................................................................. 35

Figure 7 4-line Serial Interface Timing............................................................................................................. 36

Figure 8 8080-series WRX Protocol ................................................................................................................ 39

Figure 9 8080-series Parallel Bus Protocol, Write to Register or Display RAM .............................................. 39

Figure 10 8080-series RDX Protocol............................................................................................................... 40

Figure 11 8080-series Parallel Bus Protocol, Read Data from Register or Display RAM............................... 40

Figure 12 6800-series Write Protocol .............................................................................................................. 42

Figure 13 6800-series Parallel Bus Protocol, Write to Register or Display RAM ............................................ 42

Figure 14 6800-series Read Protocol.............................................................................................................. 43

Figure 15 6800-series Parallel Bus Protocol, Read Data form Register or Display RAM............................... 43

Figure 16 Serial Interface Data Stream Format .............................................................................................. 44

Figure 17 3-line Serial Interface Write Protocol (Write to Register with Control Bit in Transmission)............. 45

Figure 18 4-line Serial Interface Write Protocol (Write to Register with Control Bit in Transmission)............. 45

Figure 19 3-line Serial Interface Read Protocol .............................................................................................. 46

Figure 20 4-line Serial Interface Read Protocol .............................................................................................. 47

Figure 21 Serial Bus Protocol, Write Mode–Interrupted by RESX .................................................................. 48

Figure 22 Serial Bus Protocol, Write Mode–Interrupted by CSX .................................................................... 48

Figure 23 Write Interrupts Recovery (Serial Interface).................................................................................... 49

Figure 24 Write Interrupts Recovery (Both Serial and Parallel Interface) ....................................................... 49

Figure 25 Serial Interface Pause Protocol (Pause by CSX)............................................................................ 50

Figure 26 Parallel Bus Pause Protocol (Paused by CSX)............................................................................... 50

Figure 27 Display Data RAM Organization...................................................................................................... 67

Figure 28 Data Streaming order ...................................................................................................................... 75

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