ADG431/ADG432/ADG433

REV. C

–6–

FREQUENCY – Hz

120

100

40

100

10M

1k

10k

100k

1M

80

60

VDD = +15V

VSS = –15V

VL = +5V

TPC 7. Off Isolation vs. Frequency

FREQUENCY – Hz

110

100

60

100

10M

1k

10k

100k

1M

90

80

70

VDD = +15V

VSS = –15V

VL = +5V

TPC 8. Crosstalk vs. Frequency

TRENCH ISOLATION

In the ADG431A, ADG432A and ADG433A, an insulating

oxide layer (trench) is placed between the NMOS and PMOS

transistors of each CMOS switch. Parasitic junctions, which

occur between the transistors in junction isolated switches, are

eliminated, the result being a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and NMOS

transistors from a diode that is reverse-biased under normal

operation. However, during overvoltage conditions, this diode

becomes forward biased. A silicon-controlled rectifier (SCR)

type circuit is formed by the two transistors causing a significant

amplification of the current which, in turn, leads to latch up.

With trench isolation, this diode is removed, the result being a

latch-up proof switch.

BURIED OXIDE LAYER

SUBSTRATE (BACKGATE)

T

R

E

N

C

H

T

R

E

N

C

H

T

R

E

N

C

H

P+

P+

P-CHANNEL

N+

N+

N-CHANNEL

P–

N–

VG

VD

VS

VG

VD

VS

Figure 1. Trench Isolation

APPLICATION

Figure 2 illustrates a precise, fast sample-and-hold circuit.

An AD845 is used as the input buffer while the output opera-

tional amplifier is an AD711. During the track mode, SW1 is

closed and the output VOUT follows the input signal VIN. In

the hold mode, SW1 is opened and the signal is held by the

hold capacitor CH.

Due to switch and capacitor leakage, the voltage on the hold

capacitor will decrease with time. The ADG431/ADG432/

ADG433 minimizes this droop due to its low leakage specifica-

tions. The droop rate is further minimized by the use of a

polystyrene hold capacitor. The droop rate for the circuit

shown is typically 30

µV/µs.

A second switch SW2, which operates in parallel with SW1, is

included in this circuit to reduce pedestal error. Since both

switches will be at the same potential, they will have a differen-

tial effect on the op amp AD711 which will minimize charge

injection effects. Pedestal error is also reduced by the compensa-

tion network RC and CC. This compensation network also reduces

the hold time glitch while optimizing the acquisition time. Using

the illustrated op amps and component values, the pedestal error

has a maximum value of 5 mV over the

±10 V input range. Both

the acquisition and settling times are 850 ns.

+15V

–15V

2200pF

RC

75

CC

1000pF

CH

2200pF

VOUT

ADG431

ADG432

ADG433

SW1

SW2

S

S

D

D

+15V

+5V

–15V

AD845

+15V

–15V

VIN

AD711

Figure 2. Fast, Accurate Sample-and-Hold