AD8017

–14–

REV. C

The first technique for maximum heat sinking is to use a heavy

layer of copper. 2 oz. copper will provide better heat sinking

than 1 oz. copper. Additional internal circuit layers can also be

used to more effectively remove heat, and to provide better

power and ground distribution.

There are no “ground” pins per se on the AD8017 (when run

on a dual supply), but the power supplies (Pins 4 and 8) are at

ac ground. Thus, these pins can be safely tied to a maximum

area of copper foil without affecting the ac performance of the

part. On the surface side of the board, the copper area that

connects to Pins 4 and 8 should be enlarged and spread out to

the maximum extent possible. As a practical matter, there will

be diminishing returns from adding copper more than a few

centimeters from the pins.

When the power supplies are run on the board on internal

power planes, then these should also be made as large as practi-

cal, and multiple vias (~0.012 in. or 0.3 mm) should be provided

from the component layer near the power supply pins of the

AD8017 to the inner layers. These vias should not have any of

the traditional “thermal relief” spokes to the planes, because the

function of these is to impede heat flow for ease of soldering.

This is counter to the effect desired for heat sinking.

On the side of the board opposite the component, additional

heat sinking can be provided by adding copper area near the vias

to further lower the thermal resistance. Additional vias can be

provided throughout to better conduct heat from the inner layers

to the outer layers.

The remainder of the device pins are active signal pins and must

be treated a bit more carefully. Pins 2 and 6 are the summing

junctions of the op amps and will be the most adversely affected by

stray capacitance. For this reason, the copper area of these pins

should be minimized. In addition, the copper nearby on the

component layer should be kept more than 3 mm–5 mm away

from these pins, where possible. The inner and opposite side

circuit layers directly below the summing junctions should also

be void of copper.

The positive inputs and outputs can withstand somewhat more

capacitance than the summing junctions without adversely

affecting ac performance. However, these pins should be treated

carefully, and the amount of heat sinking and excess capacitance

should be analyzed and adjusted depending on the application.

If maximum ac performance is desired and the power dissipa-

tion is not extreme, then the copper area connected to these pins

should be minimized. If the ac performance is not very critical

and maximum power must be dissipated, then the copper area

connected to these pins can be increased. As in many other

areas of analog design, the designer must use some judgment

based on the consideration of the above, in order to produce a

satisfactory design.

LAYOUT CONSIDERATIONS

The specified high speed performance of the AD8017 requires

careful attention to board layout and component selection.

Table II shows recommended component values for the AD8017

and Figures 10–12 show recommended layouts for the 8-lead

SOIC package for a positive gain. Proper RF design techniques

and low parasitic component selections are mandatory.

Table II. Typical Bandwidth vs. Gain Setting Resistors

)

Small Signal

Gain

–3 dB BW (MHz)

–1

619

619

54.5

110

+1

619

49.9

320

+2

619

619

49.9

160

+10

619

68.8

49.9

40

Ω characteristic input impedance.

The PCB should have a ground plane covering all unused

portions of the component side of the board to provide a low

impedance ground path. The ground plane should be removed

from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see Fig-

ures 4 and 5). One end should be connected to the ground

plane and the other within 1/8 in. of each power pin. An addi-

tional (4.7

µF–10 µF) tantalum electrolytic capacitor should be

connected in parallel.

The feedback resistor should be located close to the inverting

input pin in order to keep the stray capacitance at this node to

a minimum. Capacitance greater than 1.5 pF at the inverting

input will significantly affect high speed performance when

operating at low noninverting gain.

Figure 10. Universal SOIC Noninverter Top Silkscreen