LM81 datasheet(3/33 Pages) NSC

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Block Diagram

Pin Description

Name(s)

Number

of Pins

Type

Description

A0/NTEST_OUT

Digital I/0

The lowest order programmable bit of the serial bus address. This

pin functions as an output during NAND Tree tests (board-level

connectivity testing). Refer to

SECTION 11 on NAND Tree testing.

Digital Input

The highest order programmable bit of the serial bus address.

SMBData

Digital I/O

Serial Bus bidirectional Data. Open-drain output.

SMBCLK

Digital Input

Serial Bus Clock.

FAN1-FAN2

5-6

Digital Inputs

Schmitt Trigger fan tachometer inputs.

Digital I/O

An active high input from an external circuit which latches a

Chassis Intrusion event. This line can go high without any

clamping action regardless of the powered state of the LM81.

There is also an internal open-drain output on this line, controlled

by Bit 6 of the Configuration Register (40h) or Bit 7 CI Clear

Section 3.3 and Section 9.0.

T_CRIT_A

Digital Output

Critical Temperature Alarm active low open-drain output. This pin

can be grounded when not used.

+ (+2.8V to

+3.8V)

POWER

+3.3V V

+ power. Bypass with the parallel combination of 10 µF

(electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors.

DS100072-2

LM81 Datasheet(PDF) 3 Page - National Semiconductor (TI)

LM81 Datasheet(HTML) 3 Page - National Semiconductor (TI)

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