Data Sheet

ADRF5292

THEORY OF OPERATION

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Rev. A | 13 of 15

The ADRF5292 integrates a driver to perform logic functions inter-

nally and to provide the advantage of a simplified CMOS-/LVTTL-

compatible control interface. There are two digital control input pins

(V1 and V2) that determine which RF port is in the insertion loss

state and which RF port is in the isolation state. See Table 7 for the

control voltage truth table.

Table 7. Control Voltage Truth Table

V1

V2

RFC to RF1

RFC to RF2

RFC to RF3

RFC to RF4

Low

Low

On

Off

Off

Off

High

Low

Off

On

Off

Off

Low

High

Off

Off

On

Off

High

High

Off

Off

Off

On

RF INPUT AND OUTPUT

The RF pins (RFC and RF1 to RF4) are DC-coupled, and DC

blocking capacitors are required on the RF lines. The RF ports are

internally matched to 50Ω. Therefore, external matching networks

are not required.

The insertion loss path conducts the RF signal between the select-

ed RF throw port and the RF common port. The isolation path

provides high loss between the insertion loss path and the unselect-

ed RF throw port that is terminated to an internal 50Ω resistor.

The ADRF5292 is bidirectional with equal power handling capabili-

ties. The RF input signal can be applied to the RFC port or the

selected RF throw port.

POWER SUPPLY

The ADRF5292 requires a positive supply on the VDD pin. Bypass-

ing capacitors are recommended on the supply lines to minimize

RF coupling.

The power-up sequence is as follows:

1. Connect to GND.

2. Power up VDD.

3. Apply the digital control inputs. The relative order of the logic

control inputs is not important. Powering the digital control

inputs before VDD can inadvertently forward bias and damage

ESD protection structures. To avoid this damage, use a series

1kΩ resistor to limit the current flowing into the digital control

pins. Use pull-up or pull-down resistors if the controller is in a

high impedance state after VDD is powered up and the control

pins are not driven to a valid logic state.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.