W191

Rev 1.0, November 20, 2006

Page 2 of 9

Overview

The W191 is a skew controlled fanout buffer optimized for

interface with registered DIMMs.

Functional Description

Output Drivers

The W191 output buffers are CMOS type which deliver a

rail-to-rail (GND to VDD) output voltage swing into a nominal

capacitive load. Thus, output signaling is both TTL and CMOS

level compatible. Nominal output buffer impedance is 15 .

Serial Control

Serial control data is written to the W191 in ten bytes of eight

bits each. Bytes are written in the order shown in Table 1

Writing Data Bytes

Each bit in the data bytes control a particular device function.

Bits are written MSB (most significant bit) first, which is bit 7.

Table 1 gives the bit formats for registers located in Data

Bytes 0-2.

Pin Definitions

Pin Name

Pin No.

Pin

Type

Pin Description

SDRAM0:5

1, 3, 6,

11, 13, 15

O

SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a

rising input edge to a rising output edge is 2.5 to 5 ns. All outputs are skew controlled

to within ±150 ps of each other.

BUF_IN

4

I

Clock Input: This clock input has an input threshold voltage of 1.5V (typ).

SDATA

8

I/O

SMBus Data input: Data should be presented to this input as described in the SMBus

section of this data sheet. Internal 250-k

pull-up resistor.

SCLOCK

9

I

SMBus clock input: The SMBus Data clock should be presented to this input as

described in the SMBus section of this data sheet. Internal 250-k

pull-up resistor.

VDDQ3

7, 12, 16

P

Power Connection: Power supply for core logic and output buffers. Connected to

3.3V supply.

GND

2, 5, 10,

14

G

Ground Connection: Connect all ground pins to the common system ground plane.

Table 1. Byte Writing Sequence

Byte

Sequence

Byte Name

Bit Sequence

Byte Description

1

Slave Address

11010010

Commands the W191 to accept the bits in Data Bytes 0-6 for internal

register configuration. Since other devices may exist on the same

common serial data bus, it is necessary to have a specific slave address

for each potential receiver. The slave receiver address for the W191 is

11010010. Register setting will not be made if the Slave Address is not

correct (or is for an alternate slave receiver).

2

Command Code

Don’t Care

Unused by the W191, therefore bit values are ignored (don’t care). This

byte must be included in the data write sequence to maintain proper byte

allocation. The Command Code Byte is part of the standard serial

communication protocol and may be used when writing to another

addressed slave receiver on the serial data bus.

3

Byte Count

Don’t Care

Unused by the W191, therefore bit values are ignored (don’t care). This

byte must be included in the data write sequence to maintain proper byte

allocation. The Byte Count Byte is part of the standard serial communi-

cation protocol and may be used when writing to another addressed slave

receiver on the serial data bus.

4

Data Byte 0

Refer to

Table 2

The data bits in these bytes set internal W191 registers that control device

operation. The data bits are only accepted when the Address Byte bit

sequence is 11010010, as noted above. For description of bit control

functions, refer to Table 2.

5

Data Byte 1

6

Data Byte 2

7

Data Byte 3

Don’t Care

8

Data Byte 4

9

Data Byte 5

10

Data Byte 6