CLC030 datasheet(19/29 Pages) NSC

19 / 29 page

Device Operation (Continued)

bit in the configuration and control registers. If a checksum

error is detected (calculated and received checksums do not

match) and the ANC Checksum Force bit is set, a new

checksum will be inserted in the ancillary data replacing the

previous one. If a checksum error is detected and the ANC

Checksum Force bit is not set, the checksum mismatch is

reported via the ANC CHECKSUM ERROR bit in the control

registers.

The ANC Checksum Error bit indicates that the received

ancillary data checksum did not agree with the CLC030’s

internally generated checksum. This bit is available as an

output on the multifunction I/O port.

ANC REGISTERS 1 THROUGH 4 (Address 05h through

08h)

Admission of ancillary data packets into the FIFO can be

controlled by the ANC MASK[15:0] and ANC ID[15:0] bits in

the control registers. The ANC ID[7:0] register can be set to

a valid 8-bit Data Identification (DID) code used for compo-

nent ancillary data packet identification as specified in

SMPTE 291M. Similarly, theANC ID[15:8] register can be

set to a valid 8-bit Secondary Data Identification (SDID) or

Data Block Number (DBN) code. The ANC MASK[7:0] is an

8-bit word that can be used to selectively control loading of

packets with specific DIDs (or DID ranges) into the FIFO.

Similarly, the ANC MASK[15:8] is an 8-bit word that can be

used to selectively control loading of packets with specific

SDID or DBNs (or SDID or DBN ranges).

When ANC MASK[7:0] or ANC MASK[15:8] is set to FFh,

packets with any DID, SDID or DBN can be loaded into the

FIFO. When any bit or bits of ANC MASK[7:0] or ANC

MASK[15:8] are set to a logic-1, the corresponding bit or bits

of ANC ID[7:0] or ANC ID[15:8], respectively are a don’t-

care when matching IDs of incoming packets. When ANC

MASK[7:0] or ANC MASK[15:8] is set to 00h, the DID,

SDID or DBN of incoming packets must match exactly, bit-

for-bit, the setting of ANC ID[7:0] or ANC ID[15:8] in the

control register for the packets to be loaded into the FIFO.

The initial value of ANC MASK[7:0] and ANC MASK[15:8]

is FFh. The initial value of ANC ID[7:0] and ANC ID[15:8] is

00h.

Bits 7 through 0 of Register ANC 1, ANC ID[7:0], and

through 0 of Register ANC2, ANC ID[15:8], and Register

ANC 4, ANC MASK[15:8], affect SDID[7:0] or DBN[7:0].

ANC REGISTER 5 (Address 17h)

The FIFO INSERT ENABLE bit enables insertion of ancillary

data stored in the FIFO into the serial data stream. Data

insertion is enabled when this bit is set to a logic-1. This bit

can be used to delay automatic insertion of data into the

serial data stream.

The CLC030 can keep track of up to 8 ancillary packets in

the FIFO. Incoming packet length versus available space in

the FIFO is also tracked. The MSG TRACK bit in the control

registers, when set, enables tracking of packets in the FIFO.

MSG TRACK also enables other functions for control of

packet traffic in the FIFO: FIFO FLUSH DYN and MSG

FLUSH DYN.

With message tracking enabled and FIFO FLUSH DYN set

to a logic-1, if a FIFO full condition is encountered when

attempting to load a packet, all existing message packets in

the FIFO will be flushed. The current message packet will be

left intact. When FIFO FLUSH DYN is not set and a FIFO full

condition is encountered, the FIFO will overrun and the FIFO

OVERRUN flag will be set. FIFO FLUSH DYN remains set

until cleared.

Setting the FIFO FLUSH STAT bit to a logic-1 flushes the

FIFO. Data may not be loaded into the FIFO during FIFO

FLUSH STAT execution. Similarly, FIFO FLUSH STAT may

not be set when data is being input to the FIFO. FIFO

FLUSH STAT is automatically reset after this operation is

complete.

With message tracking enabled and MSG FLUSH DYN set

to a logic-1, the oldest message packet in the FIFO will be

flushed when the next message is written to the FIFO. MSG

FLUSH DYN remains set until cleared.

When MSG FLUSH STAT is set to a logic-1, the oldest

message packet in the FIFO is flushed when data is not

being written to the FIFO. MSG FLUSH STAT is automati-

cally reset after this operation is complete.

The FULL MSG REQ (full message required) bit in the

control registers, when set, instructs the CLC030 to insert

only complete packets residing in the FIFO into the serial

data stream. When this bit is not set, incomplete or partial

messages of any length up to the maximum buffer length will

be inserted into the serial data stream. This function is not

affected by MSG TRACK. This function can be used to

prevent overrunning available space in the FIFO.

Execution of these FIFO operations requires toggling of

ACLK.

ANC REGISTER 6 (Addresses 18h)

The ANC PARITY MASK bit when set disables parity check-

ing for the DATA ID (DID) and SECONDARY DATA ID (SDID)

or Data Block Number (DBN) in the ANC data packet. When

reset, parity checking is enabled, and, if a parity error occurs,

the packet will not be loaded.

The VANC bit in the control registers, when set to a logic-1,

enables insertion of ancillary data during the vertical blank-

ing interval.

SWITCH POINT REGISTERS 0 THROUGH 3 (Addresses

09h, 0Ah, 19h and 1Ah)

The Line[10:0] and Protect[4:0] bits define the vertical

switching point line and number of protected lines following

the switching point line for fields 0 and 1 (or fields 1 and 2 as

these are sometimes referred to) of high-defination formats.

The vertical switching point for component digital standard

definition formats is defined in SMPTE RP 168-1993. The

vertical switching point for high-definition formats has the

same basic definition. However, since the vertical switching

point lines are not necessarily standardized among the vari-

ous high-definition rasters, these registers provide a conve-

nient means whereby the vertical switching point line and

subsequent protected lines may be specified by the user.

The Switch Point registers do not operate for standard defi-

nition formats.

The Line[10:0] bits of registers Switch Point 0 and 1 may

be loaded with a line number ranging from 0 to 1023 which

then specifies the switching point line for Field 0. The Pro-

tect[4:0] bits of register Switch Point 1 determine the num-

ber of lines from 0 to 15 after the vertical switching point line

in which ancillary data may not be inserted. LINE(0) is the

LSB and LINE(10) is the MSB for the Line[10:0] bits. Similar

ordering holds for the Protect[4:0] bits.

The Line[10:0] and Protect[4:0] bits of registers Switch

Point 2 and 3 perform the same function as explained above

for the vertical switching point line for Field 1.

CLC030 Datasheet(PDF) 19 Page - National Semiconductor (TI)

CLC030 Datasheet(HTML) 19 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL