CLC030 datasheet(20/29 Pages) NSC

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Device Operation (Continued)

FORMAT REGISTERS 0 (Addresses 0Bh)

The CLC030 may be set to process a single video format by

writing the appropriate data into the FORMAT 0 register. The

Format Set[4:0] bits confine the CLC030 to recognize and

process only one of the fourteen specified types of standard

or high definition formats. When the CLC030 is set to pro-

cess a single format, it will not recognize and therefore will

not process other formats that it is capable of recognizing.

The Format Set[4:0] bits may not be used to confine device

operation to a range of standards. For normal operating

situations, it is recommended that the CLC030 be operated

in automatic format detection mode, i.e. that the Format 0

The available formats and codes are detailed in Table 4.

Generally speaking, the Format Set[4:0] codes indicate or

group the formats as follows: Format Set[4] is set for the HD

formats and reset for the SD formats. Format Set[3] when

set indicates that PAL data is being processed. When reset

NTSC data is being processed. Format Set[2:0] correspond

to one of the sub-standards given in the table. Note that the

CLC030 makes no distinction in formats resulting from the

processing of data at 74.25MHz or 74.176MHz.

The HD Only bit when set to a logic-1 locks the CLC030 into

the high definition data range and frequency. In systems

designed to handle only high definition signals, enabling HD

Only reduces the time required for the CLC030 to establish

frequency lock and determine the HD format being pro-

cessed.

The SD Only bit when set to a logic-1 locks the CLC030 into

the standard definition data ranges and frequencies. In sys-

tems designed to handle only standard definition signals,

enabling SD Only reduces the time required for the CLC030

to establish frequency lock and determine the format being

processed. When SD Only and HD Only are set to logic-0,

the device operates in SD/HD mode.

TABLE 4. Video Raster Format Parameters

Format

Code

[4,3,2,1,0]

Format

Specification

Frame

Rate

Lines

Active Lines

Samples

Active

Samples

00001

SDTV, 54

SMPTE 344M

60I

525

507/487

3432

2880

00010

SDTV, 36

SMPTE 267M

60I

525

507/487

2288

1920

00011

SDTV, 27

SMPTE 125M

60I

525

507/487

1716

1440

01001

SDTV, 54

ITU-R BT

601.5

50I

625

577

3456

2880

01010

SDTV, 36

ITU-R BT

601.5

50I

625

577

2304

1920

01011

SDTV, 27

ITU-R BT

601.5

50I

625

577

1728

1440

10001

HDTV, 74.25

SMPTE 260M

30I

1125

1035

2200

1920

10010

HDTV, 74.25

SMPTE 274M

30I

1125

1080

2200

1920

10011

HDTV, 74.25

SMPTE 274M

30P

1125

1080

2200

1920

11001

HDTV, 74.25

SMPTE 274M

25I

1125

1080

2640

1920

11010

HDTV, 74.25

SMPTE 274M

25P

1125

1080

2640

1920

11100

HDTV, 74.25

SMPTE 295M

25I

1250

1080

2376

1920

11101

HDTV, 74.25

SMPTE 274M

24P

1125

1080

2750

1920

10100

HDTV, 74.25

SMPTE 296M

60P

750

720

1650

1280

FORMAT REGISTER 1 (Address 0Ch)

The CLC030 can automatically determine the format of the

incoming parallel data. The result of this operation is stored

in the FORMAT 1 register. The Format[4:0] bits identify

which of the many possible video data standards that the

CLC030 can process is being received. These format codes

follow the same arrangement as for the Format Set[4:0]

bits. These formats and codes are given in Table 4. Bit

Format[4] when set indicates that HD data is being pro-

cessed. When reset, SD data is indicated. Format[3] when

set indicates that PAL data is being processed. When reset

NTSC data is being processed. Format[2:0] correspond

with one of the sub-standards given in the table.

The H, V, and F bits register correspond to input TRS data

bits 6, 7 and 8, respectively. The meaning and function of

this data is the same for both standard definition (SMPTE

125M) and high definition (SMPTE 292M luminance and

color difference) video data. Polarity is logic-1 equals HIGH-

true. These bits are registered for the duration of the appli-

cable field.

TEST 0 REGISTER (Address 0Dh)

The Test Pattern Select bits determine which test pattern is

output when the Test Pattern Generator (TPG) mode or the

Built-in Self-Test (BIST) mode is enabled. Table 5 gives the

codes corresponding to the various test patterns. All HD

color bars test patterns are BIST data. Standard Definition

BIST test patterns are: NTSC, 27MHz, 4x3 color Bars and

PAL, 27MHz, 4x3 PLL Pathological.

The TPG Enable bit when set to a logic-1 enables the Test

Pattern Generator function and built-in self-test (BIST). This

bit is mapped to I/O port bit 7 in the default condition. Note

that the input pulldown on the I/O port bit has the effect of

overriding the logic level of data being written into the regis-

ter via the ancillary/Control Data Port. In cases where it is

desired to control the state of TPG Enable through the

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