PCA9537DP datasheet(12/25 Pages) NXP

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NXP Semiconductors

PCA9537

4-bit I2C-bus and SMBus low power I/O port with interrupt and reset

Standard-

mode I2C-bus

Fast-mode I2C-bus

Symbol Parameter

Conditions

Min

Max

Min

Max

Unit

tHD;STA

hold time (repeated) START condition

4.0

0.6

μs

tSU;STA

set-up time for a repeated START

condition

4.7

0.6

μs

tSU;STO

set-up time for STOP condition

4.0

0.6

μs

tHD;DAT

data hold time

tVD;ACK

data valid acknowledge time

[1]

0.3

3.45

0.1

0.9

μs

tVD;DAT

data valid time

[2]

300

tSU;DAT

data set-up time

250

100

tLOW

LOW period of the SCL clock

4.7

1.3

μs

tHIGH

HIGH period of the SCL clock

4.0

0.6

μs

rise time of both SDA and SCL signals

1000

20 + 0.1Cb[3]

300

fall time of both SDA and SCL signals

300

20 + 0.1Cb[3]

300

tSP

pulse width of spikes that must be

suppressed by the input filter

Port timing

tv(Q)

data output valid time

200

tsu(D)

data input set-up time

100

th(D)

data input hold time

μs

Interrupt timing

tv(INT)

valid time on pin INT

μs

trst(INT)

reset time on pin INT

μs

RESET

tw(rst)

reset pulse width

trec(rst)

reset recovery time

trst

reset time

400

Table 11. Dynamic characteristics...continued

[1]

tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2]

tVD;DAT = minimum time for the SDA data out to be valid following SCL LOW.

[3]

Cb = total capacitance of one bus line in pF.

PCA9537

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 8 September 2021

COMPANY PUBLIC

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