L6917B

16/33

voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-

imate response time for

∆I load transient in case of enough fast compensation network response:

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst

case is the response time after removal of the load with the minimum output voltage programmed and the max-

imum input voltage available.

MAIN CONTROL LOOP

The L6917B control loop is composed by the Current Sharing control loop and the Average Current Mode con-

trol loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its

regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current

Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 10 reports the

block diagram of the main control loop.

Figure 10. Main Control Loop Diagram

t

a pplic atio n

LI

∆

⋅

V

IN

V

OUT

–

------------------------------

=

t

rem ov al

LI

∆

⋅

V

OUT

---------------

=

0

1

2

3

4

5

6

7

8

9

0.5

1.5

2.5

3.5

Output Voltage [V]

L=3

µH,

Vin=12V

L=2

µH,

Vin=12V

L=1.5

µH, Vin=12V

L=2

µH,

Vin=5V

L=1.5

µH,

Vin=5V

L=3

µH, Vin=5V

L1

L2

+

+

PWM1

1/5

+

-

1/5

4/5

PWM2

FB

COMP

ERROR

AMPLIFIER

REFERENCE

PROGRAMMED

BY VID

CURRENT

SHARING

DUTY CYCLE

CORRECTION

D02IN1392