LMX9301 datasheet(7/10 Pages) NSC

7 / 10 page

Functional Description (Continued)

PULSE SWALLOW FUNCTION

fVCO e (P c B) a A c fOSC R where fOSC e 30 kHz

fVCO

Output frequency of voltage controlled oscillator (VCO) 738 MHz to 766 MHz

Preset divide ratio of binary 11-bit programmable counter

If P e 128 then 192 s B s 199

If P e 64 then 384 s B s 399

Preset divide ratio of binary 7-bit swallow counter (0 s A s 127 A s B)

If P e 128 then 0 s A s 127

If P e 64 then 0 s A s 64

fOSC

Output frequency of the external reference frequency oscillator

Preset divide ratio of binary 14-bit programmable reference counter (3 to 1333)

Preset modulus of dual modulus prescaler

SERIAL DATA INPUT TIMING

TLW12822 – 8

Notes

Parenthesis data indicates programmable reference divider data

Data shifted into register on clock rising edge

Data is shifted in MSB first

Test Conditions

The Serial Data Input Timing is tested using a symmetrical waveform around VCC 2 The test waveform has an edge rate of 06 Vns with

amplitudes of 22V

VCC e 27V and 26V

VCC e 55V

Typical Lock Detect Circuit

A lock detect circuit is needed in order to provide a steady LOW signal when the PLL is in the locked state A typical circuit is

shown below

TLW12822 – 9

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LMX9301 Datasheet(PDF) 7 Page - National Semiconductor (TI)