AD4083BBCZ datasheet(22/94 Pages) AD

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Data Sheet

AD4083

THEORY OF OPERATION

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Figure 36. Typical Regulator Start-Up Transient, Converter Idle

All supply domains are internally decoupled using multilayer, high

dielectric, ceramic capacitors (X6S), eliminating the need of exter-

nal decoupling capacitors. However, care must be taken to under-

stand the bulk decoupling requirements for other components in the

design that share the same supply. Integrated supply decoupling

capacitors in the AD4083 are listed in Table 6 as well as in Table 9.

Table 9. Integrated Supply Decoupling Summary

Supply Pin

Nominal Value (μF)

Tolerance (%)

Return Path

VDD33

0.47

±10

GND

VDDLDO

0.22

±10

GND

VDD11

1.88 (4× 0.47)

±10

GND

IOVDD

0.22

±10

IOGND

INTERNALLY REGULATED SUPPLY

CONFIGURATION

The AD4083 includes two internal LDO regulators, one to generate

the 1.1V VDD11 supply rail and another to internally generate the

1.1V IOVDD supply rail. Upon power on or reset of the AD4083

registers, both regulators automatically power up when an external

voltage source in the range of 1.4V to 2.7V is applied to the

VDDLDO pin. The regulators are designed to supply the internal

load requirement of the AD4083; therefore, no external loading is

permitted. Note that, as described in the Power Saving Operating

Modes section, IOVDD is disabled in both power saving modes.

The required connectivity when using the internal regulators is

illustrated in Figure 37. As shown in Figure 37, the VDD11 pins

(A1, A2, and A3) must be shorted together. It is recommended that

a thick trace or polygon on the device side of the PCB be used

to implement this connection in the physical design to minimize

routing impedance. The VDD33 rail is supplied with an external

3.3V supply. This supply can be removed when using power saving

modes. When this supply is removed, only analog circuity is held

in reset, and the configuration register content remains unaffected.

Refer to Table 1 for the applicable input voltage tolerance for each

supply rail.

Figure 37. Internally Regulated (1.1V) Supply Configuration

The internally regulated configuration is ideal for use in area con-

strained applications where the ability to eliminate external regula-

tors is advantageous. However, note that, in this configuration, the

internal supply regulation introduces additional power dissipation.

EXTERNALLY GENERATED SUPPLY

CONFIGURATION

In system using externally generated supplies VDDLDO must be

left unconnected. With VDDLDO unconnected both the internal

LDO powering VDD11 and the internal LDO powering IOVDDD are

automatically disabled. VDD11 must be connected to an externally

generated 1.1V supply rail, and IOVDD should be connected to an

externally generated 1.1V to 1.2V supply rail. It should be noted

that if VDD11 is not present, the device will be held in a power-on

reset (POR) state, and all AD4083 registers reset to their default

state after the supply has been reestablished. More details on the

POR circuitry can be found in the Power-On Reset (POR) Monitor

section. The VDD33 rail is supplied with an external 3.3V supply.

The VDD33 supply can be removed to further reduce power (see

the Power Saving Operating Modes section), only analog circuity is

held in reset, and the register content remains unaffected. Refer to

Table 1 for the applicable input voltage tolerance for each supply

rail.

As illustrated in the example of Figure 38, external voltage sources

are applied to VDD11 and IOVDD pins.

Figure 38. Externally Sourced Supply Configuration

POWER-ON RESET (POR) MONITOR

The AD4083 power supply monitoring circuits inhibit the converter

functions and reset the configuration memory when supply con-

ditions are outside the specified operating limits. This function

ensures each device is in a deterministic state after power-up.

The power-on function is constructed from two independent voltage

monitors, the first measuring the core 1.1V supply and a second

AD4083BBCZ Datasheet(PDF) 22 Page - Analog Devices

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