SSD1805 Series
Rev 1.1
P 13/52
Jun 2004
Solomon Systech
6.23 C68/ 80
This pin is MCU parallel interface selection input. When the pin is pulled high, 6800 series interface is
selected and when the pin is pulled low, 8080 series interface is selected. If Serial Interface is selected (P/ S
pulled low), the setting of this pin is ignored, but it must be connected to a known logic (either high or low).
6.24 P/ S
This pin is serial/parallel interface selection input. When this pin is pulled high, parallel interface mode is
selected. When it is pulled low, serial interface will be selected.
Note1: For serial mode, R/W( WR ) must be connected to Vss. E/( RD ) must be connected to VDD. D0 to D5
and C68/80 can be connected to either VDD or VSS.
Note2: Read Back operation is only available in parallel mode.
6.25 /HPM
This pin is the control input of High Power Current Mode. The function of this pin is only enabled for High
Power model, which required special ordering. For normal models, High Power Mode is disabled.
Note: This pin must be pulled to high. Leaving this pin floating is prohibited.
6.26 IRS
This is the input pin to enable the internal resistors network for the voltage regulator. When this pin is pulled
high, the internal feedback resistors of the internal regulator for generating VOUT will be enabled. When it is
pulled low, external resistors, R1 and R2, should be connected to VSS and VF, and VF and VOUT, respectively
(see application circuit diagrams).
6.27 C1, C0
These pins are the Chip Mode Selection input. The chip mode is determined by multiplex ratio. Altogether
there are four chip modes. Please see the following list for reference.
C1
C0
Chip Mode
0
0
32 MUX Mode
0
1
54 MUX Mode
1
0
64 MUX Mode
1
1
68 MUX Mode
Please refer to Table 3 on page 15 for detail description of common pins at different multiplex mode.
6.28 B1, B0
These pins are the Chip Mode Selection input. The chip mode is determined by default boosting level.
Altogether there are four chip modes. Please see the following list for reference.
B1
B0
Chip Mode
0
0
3X as POR default
0
1
4X as POR default
1
0
5X as POR default
1
1
2X as POR default
5X, 4X, 3X or 2X booster level can be selected as POR default value of the device.
6.29 ROW0 to ROW67
These pins provide the Common driving signals to the LCD panel. See Table 3 on page 15 for the COM
signal mapping in different multiplex mode of SSD1805. There are ICON pins on the chip when either 64 or
54 or 32 Mux mode is selected. The ICON pins are located at the COM 0 pin and COM 67 pin.
6.30 SEG0 to SEG131
These pins provide the LCD segment driving signals. The output voltage level of these pins is VSS during
sleep mode and standby mode.
6.31 TEST0
This pin is a test pin. It is recommended to connect to VSS in normal operation.
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