AD5372/AD5373

Rev. C | Page 5 of 28

Parameter

AD53721

B Version

AD53731

B Version

Unit

Test Conditions/Comments2

POWER REQUIREMENTS

DVCC

2.5/5.5

2.5/5.5

V min/V max

VDD

9/16.5

9/16.5

V min/V max

VSS

−16.5/−4.5

−16.5/−4.5

V min/V max

Power Supply Sensitivity2

∆Full Scale/∆VDD

−75

−75

dB typ

∆Full Scale/∆VSS

−75

−75

dB typ

∆Full Scale/∆DVCC

−90

−90

dB typ

DICC

2

2

mA max

DVCC = 5.5 V, VIH = DVCC, VIL = GND

IDD

16

16

mA max

Outputs unloaded, DAC outputs = 0 V

18

18

mA max

Outputs unloaded, DAC outputs = full scale

ISS

−16

−16

mA max

Outputs unloaded, DAC outputs = 0 V

−18

−18

mA max

Outputs unloaded, DAC outputs = full scale

Power-Down Mode

Bit 0 in the control register is 1

DICC

5

5

μA typ

IDD

35

35

μA typ

ISS

−35

−35

μA typ

Power Dissipation (Unloaded)

250

250

mW typ

VSS = −8 V, VDD = 9.5 V, DVCC = 2.5 V

Junction Temperature3

130

130

°C max

TJ = TA + PTOTAL × θJA

1 Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.

2 Guaranteed by design and characterization; not production tested.

3 θJA represents the package thermal impedance.

AC CHARACTERISTICS

DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),

offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter

B Version

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE1

Output Voltage Settling Time

20

μs typ

Full-scale change

30

μs max

DAC latch contents alternately loaded with all 0s and all 1s

Slew Rate

1

V/μs typ

Digital-to-Analog Glitch Energy

5

nV-s typ

Glitch Impulse Peak Amplitude

10

mV max

Channel-to-Channel Isolation

100

dB typ

VREF0, VREF1 = 2 V p-p, 1 kHz

DAC-to-DAC Crosstalk

10

nV-s typ

Digital Crosstalk

0.2

nV-s typ

Digital Feedthrough

0.02

nV-s typ

Effect of input bus activity on DAC output under test

Output Noise Spectral Density @ 10 kHz

250

nV/√Hz typ

VREF0 = VREF1 = 0 V

1 Guaranteed by design and characterization; not production tested.