AD5372/AD5373

Rev. C | Page 21 of 28

SERIAL INTERFACE

The AD5372/AD5373 contain a high speed SPI operating at

clock frequencies up to 50 MHz (20 MHz for read operations).

To minimize both the power consumption of the device and

on-chip digital noise, the interface powers up fully only when

the device is being written to, that is, on the falling edge of

SYNC. The serial interface is 2.5 V LVTTL-compatible when

operating from a 2.5 V to 3.6 V DVCC supply. It is controlled by

four pins: SYNC (frame synchronization input), SDI (serial

data input pin), SCLK (clocks data in and out of the device),

and SDO (serial data output pin for data readback).

SPI WRITE MODE

The AD5372/AD5373 allow writing of data via the serial interface

to every register directly accessible to the serial interface, that is,

all registers except the X2A, X2B, and DAC registers. The X2A

and X2B registers are updated when writing to the X1A, X1B,

M, and C registers, and the DAC data registers are updated by

LDAC. The serial word (see

or

) is 24 bits long:

16 (AD5372) or 14 (AD5373) of these bits are data bits; six bits

are address bits; and two bits are mode bits that determine what

is done with the data. Two bits are reserved on the AD5373.

Table 11

Table 12

The serial interface works with both a continuous and a burst

(gated) serial clock. Serial data applied to SDI is clocked into

the AD5372/AD5373 by clock pulses applied to SCLK. The first

falling edge of SYNC starts the write cycle. At least 24 falling

clock edges must be applied to SCLK to clock in 24 bits of data

before SYNC is taken high again. If SYNC is taken high before

the 24th falling clock edge, the write operation is aborted.

If a continuous clock is used, SYNC must be taken high before the

25th falling clock edge. This inhibits the clock within the AD5372/

AD5373. If more than 24 falling clock edges are applied before

SYNC is taken high again, the input data becomes corrupted. If

an externally gated clock of exactly 24 pulses is used, SYNC can

be taken high any time after the 24th falling clock edge.

The input register addressed is updated on the rising edge of

SYNC. For another serial transfer to take place, SYNC must be

taken low again.

SPI READBACK MODE

The AD5372/AD5373 allow data readback via the serial

interface from every register directly accessible to the serial

interface, that is, all registers except the X2A, X2B, and DAC

data registers. To read back a register, it is first necessary to tell

the AD5372/AD5373 which register is to be read. This is achieved

by writing a word whose first two bits are the Special Function

Code 00 to the device. The remaining bits then determine which

register is to be read back.

If a readback command is written to a special function register,

data from the selected register is clocked out of the SDO pin

during the next SPI operation. The SDO pin is normally three-

stated but becomes driven as soon as a read command is issued.

The pin remains driven until the register data is clocked out.

See Figure 5 for the read timing diagram. Note that due to the

timing requirements of t22 (25 ns), the maximum speed of the

SPI interface during a read operation should not exceed 20 MHz.

REGISTER UPDATE RATES

The value of the X2A register or the X2B register is calculated

each time the user writes new data to the corresponding X1, C,

or M register. The calculation is performed by a three-stage

process. The first two stages take approximately 600 ns each, and

the third stage takes approximately 300 ns. When the write to an

X1, C, or M register is complete, the calculation process begins.

If the write operation involves the update of a single DAC

channel, the user is free to write to another register, provided

that the write operation does not finish until the first-stage

calculation is complete (that is, 600 ns after the completion of

the first write operation). If a group of channels is being updated

by a single write operation, the first-stage calculation is repeated

for each channel, taking 600 ns per channel. In this case, the

user should not complete the next write operation until this time

has elapsed.

Table 11. AD5372 Serial Word Bit Assignment

I23

I22

I21

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

I0

M1

M0

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Table 12. AD5373 Serial Word Bit Assignment

I23

I22

I21

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I11

I01

M1

M0

A5

A4

A3

A2

A1

A0

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

1 Bit I1 and Bit I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0.