DALSA’s IL-P3 series of linear CCD image sensors use pro-
prietary technology to provide a single output at 40MHz.
The series employs buried channel CCD shift registers to
maximize output speed and reduce noise. The sensor has a
dynamic range of >1800:1 and provides output which is lin-
ear for the operating range of light input. The IL-P3’s expo-
sure control allows integration times shorter than the
readout time. Proprietary DALSA image sensor architec-
ture provides low image lag pixels and high blue response.
The IL-P3 sensor’s superior performance makes it ideally
suited for applications requiring maximum speed and high
resolution, such as:
n High performance document scanning
n Inspection
n Optical character recognition
Functional Description
The IL-P3 sensor is composed of three main functional
groups: surface gated photodiodes in which the signal
charge packets are generated, a single CCD readout shift
registers, and an output amplifier where the charge packets
are converted to voltage pulses.
Detection
The IL-P3 series includes sensors with 512, 1024, or 2048
pixels with active imaging area lengths of 7, 14, and 28mm,
respectively. Photoelements are 14µm square for a photo-
sensitive area of 196µm
2 and a 1:1 aspect ratio. Light inci-
dent on these photoelements is converted into charge
packets whose size (i.e., number of electrons) is linearly de-
pendent on the light intensity and the integration time. The
charge is collected into a separate storage well (VSTOR) ad-
jacent to each photoelement. This helps to minimize image
lag, nonuniformities associated with the use of pixel reset,
and crosstalk between the photodiode and the CCD shift
register.
With exposure control disabled, integration time is the pe-
riod between successive pulses of the transfer (TCK) clock.
Integration time can be further reduced with electronic ex-
posure control using the pixel reset (PR) clock. The pixel
reset clock resets not the photoelements themselves but
the storage well adjacent to each photoelement. When PR
is clocked, the integration time becomes the duration be-
tween the falling edge of the PR clock and the rising edge of
the TCK clock.
IL-P3
Line Scan Sensors
For product information and updates visit www.dalsa.com
DALSA INC.: Phone: 519-886-6000 Fax: 519-886-8023
03-36-00166-06
ISO 9001
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www.dalsa.com
OS
VDD
CR1 CR2
TCK
VSS
VSET
VOD
RST
VBB
S
I
CCD Readout Shift Register
Isolation pixels
Light-shielded pixels
N = 512,1024,or 2048
15 I
1
N Surface Gated Photodiodes (14 µm x 14 µm)
2I
1S
2I
Storage Well with Anti-blooming and Exposure Control
PR
VPR
VSTOR
1I
5S
CRLAST
Relative position of package Pin 1
1
Figure 1. IL-P3 Block Diagram
Clock Drivers
Min. # Required
Type
Speed
PR off
PR on
Low Voltage
High
2
2
Low Voltage
Low
1
2
Glitch
High
1
1
1.
Redundant clock drivers may be required to drive
the CCD input capacitance. Refer to Figure 7 for
details.
2.
PR = Pixel Reset (exposure control).
Table 2. # of Clock Drivers Required
DC Biases
# Required
Regulated?
PR off
PR on
Yes
7
7
No
1
1
1.
Refer to Figure 7 for details.
2.
PR = Pixel Reset (exposure control).
Table 3. # of DC Biases Required
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