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AD9879 Datasheet(PDF) 13 Page - Analog Devices

Part # AD9879
Description  Mixed-Signal Front End Set-Top Box, Cable Modem
PDF  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9879 Datasheet(HTML) 13 Page - Analog Devices

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AD9879
Rev. A | Page 13 of 32
An internal PLL generates the DAC sampling frequency, fSYSCLK,
by multiplying OSCIN frequency M times. The MCLK signal
(Pin 23), fMCLK, is derived by dividing fSYSCLK by 4.
fSYSCLK = fOSCIN × M
(4)
fMCLK = fOSCIN × M/4
(5)
An external PLL loop filter (Pin 57) consisting of a series
resistor and ceramic capacitor (Figure 18, R1 = 1.3 kΩ,
C12 = 0.01 µF) is required for stability of the PLL. Also, a shield
surrounding these components is recommended to minimize
external noise coupling into the PLL’s voltage controlled
oscillator input (guard trace connected to AVDDPLL).
Figure 3 shows that ADCs are either sampled directly by a low
jitter clock at OSCIN or by a clock that is derived from the PLL
output. Operating modes can be selected in Register 0x08.
Sampling the ADCs directly with the OSCIN clock requires
MCLK to be programmed to be twice the OSCIN frequency.
PROGRAMMABLE CLOCK OUTPUT REFCLK
The AD9879 provides an auxiliary output clock on Pin 71,
REFCLK. The value of the MCLK divider bit field, R,
determines its output frequency as shown:
fREFCLK = fMCLK/R, for R = 2 − 3
(6)
fREFCLK = fOSCIN/R, for R = 0
(7)
In its default setting (0x00 in Register 0x01), the REFCLK pin
provides a buffered output of fOSCIN.
2
DRGND
3
DRVDD
4
(MSB) IF(11)
7
IF(8)
6
IF(9)
5
IF(10)
1
DNC
8
IF(7)
9
IF(6)
10
IF(5)
12
IF(3)
13
IF(2)
14
IF(1)
15
IF(0)
16
(MSB) RXIQ(3)
17
RXIQ(2)
18
RXIQ(1)
19
RXIQ(0)
20
RXSYNC
21
DRGND
22
DRVDD
23
MCLK
24
DVDD
25
DGND
26
TXSYNC
27
(MSB) TXIQ(5)
28
TXIQ(4)
29
TXIQ(3)
30
TXIQ(2)
11
IF(4)
79
I+
78
I–
77
DNC
74
AGNDIQ
75
DNC
76
DNC
80
DNC
73
AVDDIQ
72
DRVDD
71
REFCLK
69
DGND
Σ-∆
68
Σ-∆

_OUT
67
FLAG1
66
DVDD
Σ- 
∆
65
CA_EN
64
CA_DATA
63
CA_CLK
62
DVDDOSC
61
OSCIN
60
XTAL
59
DGNDOSC
58
AGNDPLL
57
PLLFILT
56
AVDDPLL
55
DVDDPLL
54
DGNDPLL
53
AVDDTX
52
TX+
51
TX–
70
DRGND
PIN 1
AD9879
TOP VIEW
(Pins Down)
C3
0.1
µF
C1
0.1
µF
CP1
10
µF
C2
0.1
µF
C6
0.1
µF
C4
0.1
µF
CP2
10
µF
C5
0.1
µF
C10
20pF
C11
20pF
GUARD TRACE
C12
0.01
µF
R1
1.3k
Ω
C13
0.1
µF
RSET
4.02k
Ω
Figure 4. Basic Connection Diagram



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