GD32H757VMT7 datasheet(69/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

- 1) bits computed by SHA-1, SHA-224, SHA-256 and MD5 algorithms respectively. In HMAC

algorithm, SHA-1, SHA-224, SHA-256 or MD5 will be called twice as hash functions and

authenticating messages can be produced.

3.13.

Trigonometric Math Unit (TMU)



10 kinds of functions.



The fixed point format is configurable.



Programmable precision.



CORDIC-algorithm core: circular system and hyperbolic system, rotation pattern and

vectoring pattern.

The Trigonometric Math Unit (TMU) is a fully configurable block that execute common

trigonometric and arithmetic operations. It can be used to calculate total 10 kinds of functions.

The input/output data meet q1.31 or q1.15 fixed point format.

3.14.

Direct memory access controller (DMA)



Two AHB master interface for transferring data, and one AHB slave interface for

programming DMA.



16 channels (8 for DMA0 and 8 for DMA1) and each channel are configurable.



Support independent single, 4, 8, 16-beat incrementing burst memory and peripheral

transfer.



Support independent 8, 16, 32-bit memory and peripheral transfer.



Peripherals supported: Timers, ADC, HPDF, SPI, I2C, USART, UART, DAC, I2S, RSPDIF,

SAI, CAU, HAU, FAC, TMU, CAN and DCI.

The flexible general-purpose DMA controllers provide a hardware method of transferring data

between peripherals and/or memory without intervention from the CPU, thereby freeing up

bandwidth for other system functions. Three types of access method are supported:

peripheral to memory, memory to peripheral, memory to memory.

Two AHB master interfaces and eight four-word depth 32-bit width FIFOs are presented in

each DMA controller, which achieves a high DMA transmission performance. There are 16

independent channels in the DMA controller (8 for DMA0 and 8 for DMA1). Each channel is

assigned a specific or multiple target peripheral devices for memory access request

management. Two arbiters respectively for memory and peripheral are implemented inside to

handle the priority among DMA requests.

3.15.

Master direct memory access controller (MDMA)



16 channels, each channel supports software triggering and requests can be selected

among any request source.

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