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GD32H757VMT7 Datasheet(PDF) 130 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757VMT7 Datasheet(HTML) 130 Page - GigaDevice Semiconductor (Beijing) Inc. |
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130 / 151 page  GD32H757xx Datasheet 129 Figure 4-12. I2S timing diagram - master mode tCK D[0] D[0] tH tL tSU(SD_MR) tH(SD_MR) tv(SD_MT) th(SD_MT) CPOL=0 CPOL=1 WS output SD transmit SD receive tV(WS) tH(WS) Figure 4-13. I2S timing diagram - slave mode tCK D[0] D[0] tH tL tSU(SD_SR) tH(SD_SR) tv(SD_ST) th(SD_ST) CPOL=0 CPOL=1 WS input SD transmit SD receive tH(WS) tSU(WS) 4.29. USART characteristics Table 4-63. USART characteristics in Synchronous mode(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency Fplckx = 300 MHz — — 37.5 MHz |
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